looking for replacements of the hard-coded control blocks
[ieee754fpu.git] / src / add / concurrentunit.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from math import log
6 from nmigen import Module
7 from nmigen.cli import main, verilog
8
9 from singlepipe import PassThroughStage
10 from multipipe import CombMuxOutPipe
11 from multipipe import PriorityCombMuxInPipe
12
13 from fpcommon.getop import FPADDBaseData
14 from fpcommon.denorm import FPSCData
15 from fpcommon.pack import FPPackData
16 from fpcommon.normtopack import FPNormToPack
17 from fpadd.specialcases import FPAddSpecialCasesDeNorm
18 from fpadd.addstages import FPAddAlignSingleAdd
19
20
21 def num_bits(n):
22 return int(log(n) / log(2))
23
24 class FPADDInMuxPipe(PriorityCombMuxInPipe):
25 def __init__(self, num_rows, iospecfn):
26 self.num_rows = num_rows
27 stage = PassThroughStage(iospecfn)
28 PriorityCombMuxInPipe.__init__(self, stage, p_len=self.num_rows)
29
30
31 class FPADDMuxOutPipe(CombMuxOutPipe):
32 def __init__(self, num_rows, iospecfn):
33 self.num_rows = num_rows
34 stage = PassThroughStage(iospecfn)
35 CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
36
37
38 class ReservationStations:
39 """ Reservation-Station pipeline
40
41 Input: num_rows - number of input and output Reservation Stations
42
43 Requires: the addition of an "alu" object, an i_specfn and an o_specfn
44
45 * fan-in on inputs (an array of FPADDBaseData: a,b,mid)
46 * ALU pipeline
47 * fan-out on outputs (an array of FPPackData: z,mid)
48
49 Fan-in and Fan-out are combinatorial.
50 """
51 def __init__(self, num_rows):
52 self.num_rows = num_rows
53 self.inpipe = FPADDInMuxPipe(num_rows, self.i_specfn) # fan-in
54 self.outpipe = FPADDMuxOutPipe(num_rows, self.o_specfn) # fan-out
55
56 self.p = self.inpipe.p # kinda annoying,
57 self.n = self.outpipe.n # use pipe in/out as this class in/out
58 self._ports = self.inpipe.ports() + self.outpipe.ports()
59
60 def elaborate(self, platform):
61 m = Module()
62 m.submodules.inpipe = self.inpipe
63 m.submodules.alu = self.alu
64 m.submodules.outpipe = self.outpipe
65
66 m.d.comb += self.inpipe.n.connect_to_next(self.alu.p)
67 m.d.comb += self.alu.connect_to_next(self.outpipe)
68
69 return m
70
71 def ports(self):
72 return self._ports
73
74