1 """ key strategic example showing how to do multi-input fan-in into a
2 multi-stage pipeline, then multi-output fanout.
4 the multiplex ID from the fan-in is passed in to the pipeline, preserved,
5 and used as a routing ID on the fanout.
8 from random
import randint
9 from nmigen
.compat
.sim
import run_simulation
10 from nmigen
.cli
import verilog
, rtlil
14 def __init__(self
, dut
, width
, fpkls
, fpop
, vals
, single_op
, opcode
,
16 self
.cancel
= cancel
# allow (test) cancellation
20 self
.single_op
= single_op
25 self
.tlen
= len(vals
) // dut
.num_rows
27 for muxid
in range(dut
.num_rows
):
32 for i
in range(self
.tlen
):
36 if isinstance(op1
, tuple):
39 res
= self
.fpop(self
.fpkls(op1
))
40 self
.di
[muxid
][i
] = (op1
, )
42 (op1
, op2
, ) = vals
.pop(0)
43 #print ("test", hex(op1), hex(op2))
44 res
= self
.fpop(self
.fpkls(op1
), self
.fpkls(op2
))
45 self
.di
[muxid
][i
] = (op1
, op2
)
46 if hasattr(res
, "bits"):
47 self
.do
[muxid
][i
] = res
.bits
49 self
.do
[muxid
][i
] = res
# for FP to INT
51 def send(self
, muxid
):
52 rs
= self
.dut
.p
[muxid
]
53 for i
in range(self
.tlen
):
55 op1
, = self
.di
[muxid
][i
]
57 op1
, op2
= self
.di
[muxid
][i
]
58 yield rs
.valid_i
.eq(1)
59 yield rs
.data_i
.a
.eq(op1
)
60 if self
.opcode
is not None:
61 yield rs
.data_i
.ctx
.op
.eq(self
.opcode
)
62 if not self
.single_op
:
63 yield rs
.data_i
.b
.eq(op2
)
64 yield rs
.data_i
.muxid
.eq(muxid
)
65 if hasattr(rs
, "mask_i"):
66 yield rs
.mask_i
.eq(1) # TEMPORARY HACK
68 o_p_ready
= yield rs
.ready_o
71 o_p_ready
= yield rs
.ready_o
74 fop1
= self
.fpkls(op1
)
76 if hasattr(res
, "bits"):
80 print("send", muxid
, i
, hex(op1
), hex(r
),
83 fop1
= self
.fpkls(op1
)
84 fop2
= self
.fpkls(op2
)
85 res
= self
.fpop(fop1
, fop2
)
86 print("send", muxid
, i
, hex(op1
), hex(op2
), hex(res
.bits
),
89 self
.sent
[muxid
].append(i
)
91 yield rs
.valid_i
.eq(0)
92 if hasattr(rs
, "mask_i"):
93 yield rs
.mask_i
.eq(0) # TEMPORARY HACK
94 # wait until it's received
95 while i
in self
.sent
[muxid
]:
98 # wait random period of time before queueing another value
99 for i
in range(randint(0, 3)):
102 yield rs
.valid_i
.eq(0)
105 print("send ended", muxid
)
107 ## wait random period of time before queueing another value
108 #for i in range(randint(0, 3)):
111 #send_range = randint(0, 3)
115 # send = randint(0, send_range) != 0
117 def rcv(self
, muxid
):
118 rs
= self
.dut
.p
[muxid
]
122 cancel
= self
.cancel
and (randint(0, 2) == 0)
123 if hasattr(rs
, "mask_i") and len(self
.sent
[muxid
]) > 0 and cancel
:
124 todel
= self
.sent
[muxid
].pop()
125 print ("to delete", muxid
, self
.sent
[muxid
], todel
)
126 if todel
in self
.do
[muxid
]:
127 del self
.do
[muxid
][todel
]
128 yield rs
.stop_i
.eq(1)
129 print ("left", muxid
, self
.do
[muxid
])
130 if len(self
.do
[muxid
]) == 0:
133 #stall_range = randint(0, 3)
134 #for j in range(randint(1,10)):
135 # stall = randint(0, stall_range) != 0
136 # yield self.dut.n[0].ready_i.eq(stall)
138 n
= self
.dut
.n
[muxid
]
139 yield n
.ready_i
.eq(1)
141 if hasattr(rs
, "mask_i"):
142 yield rs
.stop_i
.eq(0) # resets cancel mask
144 o_n_valid
= yield n
.valid_o
145 i_n_ready
= yield n
.ready_i
146 if not o_n_valid
or not i_n_ready
:
149 out_muxid
= yield n
.data_o
.muxid
150 out_z
= yield n
.data_o
.z
152 if not self
.sent
[muxid
]:
153 print ("cancelled/recv", muxid
, hex(out_z
))
156 out_i
= self
.sent
[muxid
].pop()
158 print("recv", out_muxid
, hex(out_z
), "expected",
159 hex(self
.do
[muxid
][out_i
]))
161 # see if this output has occurred already, delete it if it has
162 assert muxid
== out_muxid
, "out_muxid %d not correct %d" % \
165 assert self
.do
[muxid
][out_i
] == out_z
167 print ("senddel", muxid
, out_i
, self
.sent
[muxid
])
168 del self
.do
[muxid
][out_i
]
170 # check if there's any more outputs
171 if len(self
.do
[muxid
]) == 0:
174 print("recv ended", muxid
)
177 def create_random(num_rows
, width
, single_op
=False, n_vals
=10):
179 for muxid
in range(num_rows
):
180 for i
in range(n_vals
):
182 op1
= randint(0, (1 << width
)-1)
198 #op1 = 0x9885020648d8c0e8
250 # f2int unsigned (fp64 to ui16)
251 #op1 = 0x40e6f5bc4d88b0cc
253 # f2int signed (fp64 to i16)
254 #op1 = 0xff292cf09f159ddb
255 #op1 = 0x5880e09f7cb716a1
257 # f2int signed (fp64 to i32)
258 #op1 = 0x5beb66ffc69a9a64
259 #op1 = 0xd4cdd178a1f2cdec
263 op1
= randint(0, (1 << width
)-1)
264 op2
= randint(0, (1 << width
)-1)
265 # op1 = 0x3F800000 # 1.0f32
266 # op2 = 0x40000000 # 2.0f32
276 vals
.append((op1
, op2
,))
280 def repeat(num_rows
, vals
):
281 """ bit of a hack: repeats the last value to create a list
282 that will be accepted by the muxer, all mux lists to be
286 n_to_repeat
= len(vals
) % num_rows
287 #print ("repeat", vals)
288 return vals
+ [vals
[-1]] * n_to_repeat
291 def pipe_cornercases_repeat(dut
, name
, mod
, fmod
, width
, fn
, cc
, fpfn
, count
,
292 single_op
=False, opcode
=None):
293 for i
, fixed_num
in enumerate(cc(mod
)):
294 vals
= fn(mod
, fixed_num
, count
, width
, single_op
)
295 vals
= repeat(dut
.num_rows
, vals
)
296 #print ("repeat", i, fn, single_op, list(vals))
297 fmt
= "test_pipe_fp%d_%s_cornercases_%d"
298 runfp(dut
, width
, fmt
% (width
, name
, i
),
299 fmod
, fpfn
, vals
=vals
, single_op
=single_op
, opcode
=opcode
)
302 def runfp(dut
, width
, name
, fpkls
, fpop
, single_op
=False, n_vals
=10,
303 vals
=None, opcode
=None, cancel
=False):
304 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
305 with
open("%s.il" % name
, "w") as f
:
309 vals
= create_random(dut
.num_rows
, width
, single_op
, n_vals
)
311 test
= MuxInOut(dut
, width
, fpkls
, fpop
, vals
, single_op
, opcode
=opcode
)
313 for i
in range(dut
.num_rows
):
314 fns
.append(test
.rcv(i
))
315 fns
.append(test
.send(i
))
316 run_simulation(dut
, fns
, vcd_name
="%s.vcd" % name
)