src/ieee754/fpdiv/div0.py

   1 """IEEE754 Floating Point Divider
   2
   3 Relevant bugreport: http://bugs.libre-riscv.org/show_bug.cgi?id=99
   4 """
   5
   6 from nmigen import Module, Signal, Cat, Elaboratable
   7 from nmigen.cli import main, verilog
   8
   9 from ieee754.fpcommon.fpbase import (FPNumBaseRecord, Overflow)
  10 from ieee754.fpcommon.fpbase import FPState
  11 from ieee754.fpcommon.denorm import FPSCData
  12 from ieee754.fpcommon.getop import FPBaseData
  13
  14
  15 class FPDivStage0Data:
  16
  17     def __init__(self, width, pspec):
  18         self.z = FPNumBaseRecord(width, False)
  19         self.out_do_z = Signal(reset_less=True)
  20         self.oz = Signal(width, reset_less=True)
  21         self.of = Overflow()
  22
  23         self.ctx = FPBaseData(width, pspec) # context: muxid, operator etc.
  24         self.muxid = self.ctx.muxid             # annoying. complicated.
  25
  26         # TODO: here is where Q and R would be put, and passed
  27         # down to Stage1 processing.
  28
  29         mw = (self.z.m_width)*2 - 1 + 3 # sticky/round/guard bits + (2*mant) - 1
  30         self.product = Signal(mw, reset_less=True)
  31
  32     def eq(self, i):
  33         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
  34                 self.of.eq(i.of),
  35                 self.product.eq(i.product), self.ctx.eq(i.ctx)]
  36
  37
  38 class FPDivStage0Mod(Elaboratable):
  39
  40     def __init__(self, width, id_wid):
  41         self.width = width
  42         self.id_wid = id_wid
  43         self.i = self.ispec()
  44         self.o = self.ospec()
  45
  46     def ispec(self):
  47         return FPSCData(self.width, self.id_wid, False)
  48
  49     def ospec(self):
  50         return FPDivStage0Data(self.width, self.id_wid)
  51
  52     def process(self, i):
  53         return self.o
  54
  55     def setup(self, m, i):
  56         """ links module to inputs and outputs
  57         """
  58         m.submodules.div0 = self
  59         m.d.comb += self.i.eq(i)
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63
  64         # XXX TODO, actual DIV code here.  this class would be
  65         # "step one" which takes the pre-normalised data (see ispec) and
  66         # *begins* the processing phase (enters the massive DIV
  67         # pipeline chain) - see ospec.
  68
  69         # NOTE: this stage does *NOT* do *ACTUAL* DIV processing,
  70         # it is PURELY the *ENTRY* point into the chain, performing
  71         # "preparation" work
  72
  73         # store intermediate tests (and zero-extended mantissas)
  74         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
  75         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
  76         m.d.comb += [
  77                      am0.eq(Cat(self.i.a.m, 0)),
  78                      bm0.eq(Cat(self.i.b.m, 0))
  79                     ]
  80         # same-sign (both negative or both positive) div mantissas
  81         with m.If(~self.i.out_do_z):
  82             m.d.comb += [self.o.z.e.eq(self.i.a.e + self.i.b.e + 1),
  83                          # TODO: no, not product, first stage Q and R etc. etc.
  84                          # go here.
  85                          self.o.product.eq(am0 * bm0 * 4),
  86                          self.o.z.s.eq(self.i.a.s ^ self.i.b.s)
  87                 ]
  88
  89         m.d.comb += self.o.oz.eq(self.i.oz)
  90         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
  91         m.d.comb += self.o.ctx.eq(self.i.ctx)
  92         return m
  93
  94
  95 class FPDivStage0(FPState):
  96     """ First stage of div.
  97     """
  98
  99     def __init__(self, width, id_wid):
 100         FPState.__init__(self, "divider_0")
 101         self.mod = FPDivStage0Mod(width)
 102         self.o = self.mod.ospec()
 103
 104     def setup(self, m, i):
 105         """ links module to inputs and outputs
 106         """
 107         self.mod.setup(m, i)
 108
 109         # NOTE: these could be done as combinatorial (merge div0+div1)
 110         m.d.sync += self.o.eq(self.mod.o)
 111
 112     def action(self, m):
 113         m.next = "divider_1"