24fd80d4cb7985588a134a8789a1b2add2d480dd
1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 dynamic-partitionable class similar to Signal, which, when the partition
8 is fully open will be identical to Signal. when partitions are closed,
9 the class turns into a SIMD variant of Signal. *this is dynamic*.
11 the basic fundamental idea is: write code once, and if you want a SIMD
12 version of it, use PartitionedSignal in place of Signal. job done.
13 this however requires the code to *not* be designed to use nmigen.If,
14 nmigen.Case, or other constructs: only Mux and other logic.
16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
19 from ieee754
.part_mul_add
.adder
import PartitionedAdder
20 from ieee754
.part_cmp
.eq_gt_ge
import PartitionedEqGtGe
21 from ieee754
.part_bits
.xor
import PartitionedXOR
22 from ieee754
.part_shift
.part_shift_dynamic
import PartitionedDynamicShift
23 from ieee754
.part_shift
.part_shift_scalar
import PartitionedScalarShift
24 from ieee754
.part_mul_add
.partpoints
import make_partition
, PartitionPoints
25 from operator
import or_
, xor
, and_
, not_
27 from nmigen
import (Signal
, Const
)
31 if isinstance(op1
, PartitionedSignal
):
36 def applyop(op1
, op2
, op
):
37 return op(getsig(op1
), getsig(op2
))
40 class PartitionedSignal
:
41 def __init__(self
, mask
, *args
, **kwargs
):
42 self
.sig
= Signal(*args
, **kwargs
)
43 width
= len(self
.sig
) # get signal width
44 # create partition points
45 if isinstance(mask
, PartitionPoints
):
46 self
.partpoints
= mask
48 self
.partpoints
= make_partition(mask
, width
)
50 for name
in ['add', 'eq', 'gt', 'ge', 'ls', 'xor']:
51 self
.modnames
[name
] = 0
53 def set_module(self
, m
):
56 def get_modname(self
, category
):
57 self
.modnames
[category
] += 1
58 return "%s_%d" % (category
, self
.modnames
[category
])
61 return self
.sig
.eq(getsig(val
))
64 def like(other
, *args
, **kwargs
):
65 """Builds a new PartitionedSignal with the same PartitionPoints and
66 Signal properties as the other"""
67 result
= PartitionedSignal(other
.partpoints
)
68 result
.sig
= Signal
.like(other
.sig
, *args
, **kwargs
)
72 # unary ops that do not require partitioning
75 result
= PartitionedSignal
.like(self
)
76 self
.m
.d
.comb
+= result
.sig
.eq(~self
.sig
)
79 # unary ops that require partitioning
82 z
= Const(0, len(self
.sig
))
83 result
, _
= self
.sub_op(z
, self
)
86 # binary ops that don't require partitioning
88 def __and__(self
, other
):
89 return applyop(self
, other
, and_
)
91 def __rand__(self
, other
):
92 return applyop(other
, self
, and_
)
94 def __or__(self
, other
):
95 return applyop(self
, other
, or_
)
97 def __ror__(self
, other
):
98 return applyop(other
, self
, or_
)
100 def __xor__(self
, other
):
101 return applyop(self
, other
, xor
)
103 def __rxor__(self
, other
):
104 return applyop(other
, self
, xor
)
106 # binary ops that need partitioning
108 # TODO: detect if the 2nd operand is a Const, a Signal or a
109 # PartitionedSignal. if it's a Const or a Signal, a global shift
110 # can occur. if it's a PartitionedSignal, that's much more interesting.
111 def ls_op(self
, op1
, op2
, carry
, shr_flag
=0):
113 if isinstance(op2
, Const
) or isinstance(op2
, Signal
):
115 pa
= PartitionedScalarShift(len(op1
), self
.partpoints
)
119 pa
= PartitionedDynamicShift(len(op1
), self
.partpoints
)
120 setattr(self
.m
.submodules
, self
.get_modname('ls'), pa
)
123 comb
+= pa
.data
.eq(op1
)
124 comb
+= pa
.shifter
.eq(op2
)
125 comb
+= pa
.shift_right
.eq(shr_flag
)
129 comb
+= pa
.shift_right
.eq(shr_flag
)
130 # XXX TODO: carry-in, carry-out
131 #comb += pa.carry_in.eq(carry)
132 return (pa
.output
, 0)
134 def __lshift__(self
, other
):
135 z
= Const(0, len(self
.partpoints
)+1)
136 result
, _
= self
.ls_op(self
, other
, carry
=z
) # TODO, carry
139 def __rlshift__(self
, other
):
140 raise NotImplementedError
141 return Operator("<<", [other
, self
])
143 def __rshift__(self
, other
):
144 z
= Const(0, len(self
.partpoints
)+1)
145 result
, _
= self
.ls_op(self
, other
, carry
=z
, shr_flag
=1) # TODO, carry
148 def __rrshift__(self
, other
):
149 raise NotImplementedError
150 return Operator(">>", [other
, self
])
152 def add_op(self
, op1
, op2
, carry
):
155 pa
= PartitionedAdder(len(op1
), self
.partpoints
)
156 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
160 comb
+= pa
.carry_in
.eq(carry
)
161 return (pa
.output
, pa
.carry_out
)
163 def sub_op(self
, op1
, op2
, carry
=~
0):
166 pa
= PartitionedAdder(len(op1
), self
.partpoints
)
167 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
170 comb
+= pa
.b
.eq(~op2
)
171 comb
+= pa
.carry_in
.eq(carry
)
172 return (pa
.output
, pa
.carry_out
)
174 def __add__(self
, other
):
175 result
, _
= self
.add_op(self
, other
, carry
=0)
178 def __radd__(self
, other
):
179 result
, _
= self
.add_op(other
, self
)
182 def __sub__(self
, other
):
183 result
, _
= self
.sub_op(self
, other
)
186 def __rsub__(self
, other
):
187 result
, _
= self
.sub_op(other
, self
)
190 def __mul__(self
, other
):
191 return Operator("*", [self
, other
])
193 def __rmul__(self
, other
):
194 return Operator("*", [other
, self
])
196 def __check_divisor(self
):
197 width
, signed
= self
.shape()
199 # Python's division semantics and Verilog's division semantics
200 # differ for negative divisors (Python uses div/mod, Verilog
201 # uses quo/rem); for now, avoid the issue
202 # completely by prohibiting such division operations.
203 raise NotImplementedError(
204 "Division by a signed value is not supported")
206 def __mod__(self
, other
):
207 raise NotImplementedError
208 other
= Value
.cast(other
)
209 other
.__check
_divisor
()
210 return Operator("%", [self
, other
])
212 def __rmod__(self
, other
):
213 raise NotImplementedError
214 self
.__check
_divisor
()
215 return Operator("%", [other
, self
])
217 def __floordiv__(self
, other
):
218 raise NotImplementedError
219 other
= Value
.cast(other
)
220 other
.__check
_divisor
()
221 return Operator("//", [self
, other
])
223 def __rfloordiv__(self
, other
):
224 raise NotImplementedError
225 self
.__check
_divisor
()
226 return Operator("//", [other
, self
])
228 # binary comparison ops that need partitioning
230 def _compare(self
, width
, op1
, op2
, opname
, optype
):
231 # print (opname, op1, op2)
232 pa
= PartitionedEqGtGe(width
, self
.partpoints
)
233 setattr(self
.m
.submodules
, self
.get_modname(opname
), pa
)
235 comb
+= pa
.opcode
.eq(optype
) # set opcode
236 if isinstance(op1
, PartitionedSignal
):
237 comb
+= pa
.a
.eq(op1
.sig
)
240 if isinstance(op2
, PartitionedSignal
):
241 comb
+= pa
.b
.eq(op2
.sig
)
246 def __eq__(self
, other
):
247 width
= len(self
.sig
)
248 return self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
250 def __ne__(self
, other
):
251 width
= len(self
.sig
)
252 eq
= self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
253 ne
= Signal(eq
.width
)
254 self
.m
.d
.comb
+= ne
.eq(~eq
)
257 def __gt__(self
, other
):
258 width
= len(self
.sig
)
259 return self
._compare
(width
, self
, other
, "gt", PartitionedEqGtGe
.GT
)
261 def __lt__(self
, other
):
262 width
= len(self
.sig
)
263 # swap operands, use gt to do lt
264 return self
._compare
(width
, other
, self
, "gt", PartitionedEqGtGe
.GT
)
266 def __ge__(self
, other
):
267 width
= len(self
.sig
)
268 return self
._compare
(width
, self
, other
, "ge", PartitionedEqGtGe
.GE
)
270 def __le__(self
, other
):
271 width
= len(self
.sig
)
272 # swap operands, use ge to do le
273 return self
._compare
(width
, other
, self
, "ge", PartitionedEqGtGe
.GE
)
278 """Conversion to boolean.
283 ``1`` if any bits are set, ``0`` otherwise.
285 return self
.any() # have to see how this goes
286 #return Operator("b", [self])
289 """Check if any bits are ``1``.
294 ``1`` if any bits are set, ``0`` otherwise.
296 return self
!= Const(0) # leverage the __ne__ operator here
297 return Operator("r|", [self
])
300 """Check if all bits are ``1``.
305 ``1`` if all bits are set, ``0`` otherwise.
307 return self
== Const(-1) # leverage the __eq__ operator here
310 """Compute pairwise exclusive-or of every bit.
315 ``1`` if an odd number of bits are set, ``0`` if an
316 even number of bits are set.
318 width
= len(self
.sig
)
319 pa
= PartitionedXOR(width
, self
.partpoints
)
320 setattr(self
.m
.submodules
, self
.get_modname("xor"), pa
)
321 self
.m
.d
.comb
+= pa
.a
.eq(self
.sig
)
324 def implies(premise
, conclusion
):
330 ``0`` if ``premise`` is true and ``conclusion`` is not,
333 # amazingly, this should actually work.
334 return conclusion | ~premise