src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  22 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
  23 from ieee754.part_mul_add.partpoints import make_partition
  24 from operator import or_, xor, and_, not_
  25
  26 from nmigen import (Signal, Const)
  27
  28
  29 def getsig(op1):
  30     if isinstance(op1, PartitionedSignal):
  31         op1 = op1.sig
  32     return op1
  33
  34
  35 def applyop(op1, op2, op):
  36     return op(getsig(op1), getsig(op2))
  37
  38
  39 class PartitionedSignal:
  40     def __init__(self, mask, *args, **kwargs):
  41         self.sig = Signal(*args, **kwargs)
  42         width = self.sig.shape()[0]  # get signal width
  43         # create partition points
  44         self.partpoints = make_partition(mask, width)
  45         self.modnames = {}
  46         for name in ['add', 'eq', 'gt', 'ge', 'ls']:
  47             self.modnames[name] = 0
  48
  49     def set_module(self, m):
  50         self.m = m
  51
  52     def get_modname(self, category):
  53         self.modnames[category] += 1
  54         return "mod_%s_%d" % (category, self.modnames[category])
  55
  56     def eq(self, val):
  57         return self.sig.eq(getsig(val))
  58
  59     # unary ops that do not require partitioning
  60
  61     def __invert__(self):
  62         return ~self.sig
  63
  64     # unary ops that require partitioning
  65
  66     def __neg__(self):
  67         result, _ = self.add_op(self, ~0, carry=0)  # TODO, subop
  68         return result
  69
  70     # binary ops that don't require partitioning
  71
  72     def __and__(self, other):
  73         return applyop(self, other, and_)
  74
  75     def __rand__(self, other):
  76         return applyop(other, self, and_)
  77
  78     def __or__(self, other):
  79         return applyop(self, other, or_)
  80
  81     def __ror__(self, other):
  82         return applyop(other, self, or_)
  83
  84     def __xor__(self, other):
  85         return applyop(self, other, xor)
  86
  87     def __rxor__(self, other):
  88         return applyop(other, self, xor)
  89
  90     # binary ops that need partitioning
  91
  92     # TODO: detect if the 2nd operand is a Const, a Signal or a
  93     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  94     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  95     def ls_op(self, op1, op2, carry):
  96         op1 = getsig(op1)
  97         if isinstance(op2, Const) or isinstance(op2, Signal):
  98             scalar = True
  99             shape = op1.shape()
 100             pa = PartitionedScalarShift(shape[0], self.partpoints)
 101         else:
 102             scalar = False
 103             op2 = getsig(op2)
 104             shape = op1.shape()
 105             pa = PartitionedDynamicShift(shape[0], self.partpoints)
 106         setattr(self.m.submodules, self.get_modname('ls'), pa)
 107         comb = self.m.d.comb
 108         if scalar:
 109             comb += pa.data.eq(op1)
 110             comb += pa.shifter.eq(op2)
 111         else:
 112             comb += pa.a.eq(op1)
 113             comb += pa.b.eq(op2)
 114         # XXX TODO: carry-in, carry-out
 115         #comb += pa.carry_in.eq(carry)
 116         return (pa.output, 0)
 117
 118     def __lshift__(self, other):
 119         result, _ = self.ls_op(self, other, carry=0)
 120         return result
 121
 122     def __rlshift__(self, other):
 123         raise NotImplementedError
 124         return Operator("<<", [other, self])
 125
 126     def __rshift__(self, other):
 127         raise NotImplementedError
 128         return Operator(">>", [self, other])
 129
 130     def __rrshift__(self, other):
 131         raise NotImplementedError
 132         return Operator(">>", [other, self])
 133
 134     def add_op(self, op1, op2, carry):
 135         op1 = getsig(op1)
 136         op2 = getsig(op2)
 137         shape = op1.shape()
 138         pa = PartitionedAdder(shape[0], self.partpoints)
 139         setattr(self.m.submodules, self.get_modname('add'), pa)
 140         comb = self.m.d.comb
 141         comb += pa.a.eq(op1)
 142         comb += pa.b.eq(op2)
 143         comb += pa.carry_in.eq(carry)
 144         return (pa.output, pa.carry_out)
 145
 146     def sub_op(self, op1, op2, carry=~0):
 147         op1 = getsig(op1)
 148         op2 = getsig(op2)
 149         shape = op1.shape()
 150         pa = PartitionedAdder(shape[0], self.partpoints)
 151         setattr(self.m.submodules, self.get_modname('add'), pa)
 152         comb = self.m.d.comb
 153         comb += pa.a.eq(op1)
 154         comb += pa.b.eq(~op2)
 155         comb += pa.carry_in.eq(carry)
 156         return (pa.output, pa.carry_out)
 157
 158     def __add__(self, other):
 159         result, _ = self.add_op(self, other, carry=0)
 160         return result
 161
 162     def __radd__(self, other):
 163         result, _ = self.add_op(other, self)
 164         return result
 165
 166     def __sub__(self, other):
 167         result, _ = self.sub_op(self, other)
 168         return result
 169
 170     def __rsub__(self, other):
 171         result, _ = self.sub_op(other, self)
 172         return result
 173
 174     def __mul__(self, other):
 175         return Operator("*", [self, other])
 176
 177     def __rmul__(self, other):
 178         return Operator("*", [other, self])
 179
 180     def __check_divisor(self):
 181         width, signed = self.shape()
 182         if signed:
 183             # Python's division semantics and Verilog's division semantics
 184             # differ for negative divisors (Python uses div/mod, Verilog
 185             # uses quo/rem); for now, avoid the issue
 186             # completely by prohibiting such division operations.
 187             raise NotImplementedError(
 188                     "Division by a signed value is not supported")
 189
 190     def __mod__(self, other):
 191         raise NotImplementedError
 192         other = Value.cast(other)
 193         other.__check_divisor()
 194         return Operator("%", [self, other])
 195
 196     def __rmod__(self, other):
 197         raise NotImplementedError
 198         self.__check_divisor()
 199         return Operator("%", [other, self])
 200
 201     def __floordiv__(self, other):
 202         raise NotImplementedError
 203         other = Value.cast(other)
 204         other.__check_divisor()
 205         return Operator("//", [self, other])
 206
 207     def __rfloordiv__(self, other):
 208         raise NotImplementedError
 209         self.__check_divisor()
 210         return Operator("//", [other, self])
 211
 212     # binary comparison ops that need partitioning
 213
 214     def _compare(self, width, op1, op2, opname, optype):
 215         # print (opname, op1, op2)
 216         pa = PartitionedEqGtGe(width, self.partpoints)
 217         setattr(self.m.submodules, self.get_modname(opname), pa)
 218         comb = self.m.d.comb
 219         comb += pa.opcode.eq(optype)  # set opcode
 220         if isinstance(op1, PartitionedSignal):
 221             comb += pa.a.eq(op1.sig)
 222         else:
 223             comb += pa.a.eq(op1)
 224         if isinstance(op2, PartitionedSignal):
 225             comb += pa.b.eq(op2.sig)
 226         else:
 227             comb += pa.b.eq(op2)
 228         return pa.output
 229
 230     def __eq__(self, other):
 231         width = self.sig.shape()[0]
 232         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 233
 234     def __ne__(self, other):
 235         width = self.sig.shape()[0]
 236         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 237         ne = Signal(eq.width)
 238         self.m.d.comb += ne.eq(~eq)
 239         return ne
 240
 241     def __gt__(self, other):
 242         width = self.sig.shape()[0]
 243         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 244
 245     def __lt__(self, other):
 246         width = self.sig.shape()[0]
 247         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 248
 249     def __ge__(self, other):
 250         width = self.sig.shape()[0]
 251         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 252
 253     def __le__(self, other):
 254         width = self.sig.shape()[0]
 255         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 256
 257     # useful operators
 258
 259     def bool(self):
 260         """Conversion to boolean.
 261
 262         Returns
 263         -------
 264         Value, out
 265             ``1`` if any bits are set, ``0`` otherwise.
 266         """
 267         raise NotImplementedError
 268         return Operator("b", [self])
 269
 270     def any(self):
 271         """Check if any bits are ``1``.
 272
 273         Returns
 274         -------
 275         Value, out
 276             ``1`` if any bits are set, ``0`` otherwise.
 277         """
 278         raise NotImplementedError
 279         return Operator("r|", [self])
 280
 281     def all(self):
 282         """Check if all bits are ``1``.
 283
 284         Returns
 285         -------
 286         Value, out
 287             ``1`` if all bits are set, ``0`` otherwise.
 288         """
 289         raise NotImplementedError
 290         return Operator("r&", [self])
 291
 292     def xor(self):
 293         """Compute pairwise exclusive-or of every bit.
 294
 295         Returns
 296         -------
 297         Value, out
 298             ``1`` if an odd number of bits are set, ``0`` if an
 299                   even number of bits are set.
 300         """
 301         # XXXX TODO: return partition-mask-sized set of bits
 302         raise NotImplementedError
 303         return Operator("r^", [self])
 304
 305     def implies(premise, conclusion):
 306         """Implication.
 307
 308         Returns
 309         -------
 310         Value, out
 311             ``0`` if ``premise`` is true and ``conclusion`` is not,
 312             ``1`` otherwise.
 313         """
 314         # amazingly, this should actually work.
 315         return ~premise | conclusion