1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 dynamic-partitionable class similar to Signal, which, when the partition
8 is fully open will be identical to Signal. when partitions are closed,
9 the class turns into a SIMD variant of Signal. *this is dynamic*.
11 the basic fundamental idea is: write code once, and if you want a SIMD
12 version of it, use PartitionedSignal in place of Signal. job done.
13 this however requires the code to *not* be designed to use nmigen.If,
14 nmigen.Case, or other constructs: only Mux and other logic.
16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
19 from ieee754
.part_mul_add
.adder
import PartitionedAdder
20 from ieee754
.part_cmp
.eq_gt_ge
import PartitionedEqGtGe
21 from ieee754
.part_mul_add
.partpoints
import make_partition
22 from operator
import or_
, xor
, and_
, not_
24 from nmigen
import (Signal
)
28 if isinstance(op1
, PartitionedSignal
):
33 def applyop(op1
, op2
, op
):
34 return op(getsig(op1
), getsig(op2
))
37 class PartitionedSignal
:
38 def __init__(self
, mask
, *args
, **kwargs
):
39 self
.sig
= Signal(*args
, **kwargs
)
40 width
= self
.sig
.shape()[0] # get signal width
41 # create partition points
42 self
.partpoints
= make_partition(mask
, width
)
44 for name
in ['add', 'eq', 'gt', 'ge']:
45 self
.modnames
[name
] = 0
47 def set_module(self
, m
):
50 def get_modname(self
, category
):
51 self
.modnames
[category
] += 1
52 return "%s%d" % (category
, self
.modnames
[category
])
55 return self
.sig
.eq(getsig(val
))
57 # unary ops that do not require partitioning
62 # unary ops that require partitioning
65 result
, _
= self
.add_op(self
, ~
0, carry
=0) # TODO, subop
68 # binary ops that don't require partitioning
70 def __and__(self
, other
):
71 return applyop(self
, other
, and_
)
73 def __rand__(self
, other
):
74 return applyop(other
, self
, and_
)
76 def __or__(self
, other
):
77 return applyop(self
, other
, or_
)
79 def __ror__(self
, other
):
80 return applyop(other
, self
, or_
)
82 def __xor__(self
, other
):
83 return applyop(self
, other
, xor
)
85 def __rxor__(self
, other
):
86 return applyop(other
, self
, xor
)
88 # binary ops that need partitioning
90 # TODO: detect if the 2nd operand is a Const, a Signal or a
91 # PartitionedSignal. if it's a Const or a Signal, a global shift
92 # can occur. if it's a PartitionedSignal, that's much more interesting.
93 def __lshift__(self
, other
):
94 raise NotImplementedError
95 return Operator("<<", [self
, other
])
97 def __rlshift__(self
, other
):
98 raise NotImplementedError
99 return Operator("<<", [other
, self
])
101 def __rshift__(self
, other
):
102 raise NotImplementedError
103 return Operator(">>", [self
, other
])
105 def __rrshift__(self
, other
):
106 raise NotImplementedError
107 return Operator(">>", [other
, self
])
109 def add_op(self
, op1
, op2
, carry
):
113 pa
= PartitionedAdder(shape
[0], self
.partpoints
)
114 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
118 comb
+= pa
.carry_in
.eq(carry
)
119 return (pa
.output
, pa
.carry_out
)
121 def sub_op(self
, op1
, op2
, carry
=~
0):
125 pa
= PartitionedAdder(shape
[0], self
.partpoints
)
126 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
129 comb
+= pa
.b
.eq(~op2
)
130 comb
+= pa
.carry_in
.eq(carry
)
131 return (pa
.output
, pa
.carry_out
)
133 def __add__(self
, other
):
134 result
, _
= self
.add_op(self
, other
, carry
=0)
137 def __radd__(self
, other
):
138 result
, _
= self
.add_op(other
, self
)
141 def __sub__(self
, other
):
142 result
, _
= self
.sub_op(self
, other
)
145 def __rsub__(self
, other
):
146 result
, _
= self
.sub_op(other
, self
)
149 def __mul__(self
, other
):
150 return Operator("*", [self
, other
])
152 def __rmul__(self
, other
):
153 return Operator("*", [other
, self
])
155 def __check_divisor(self
):
156 width
, signed
= self
.shape()
158 # Python's division semantics and Verilog's division semantics
159 # differ for negative divisors (Python uses div/mod, Verilog
160 # uses quo/rem); for now, avoid the issue
161 # completely by prohibiting such division operations.
162 raise NotImplementedError(
163 "Division by a signed value is not supported")
165 def __mod__(self
, other
):
166 raise NotImplementedError
167 other
= Value
.cast(other
)
168 other
.__check
_divisor
()
169 return Operator("%", [self
, other
])
171 def __rmod__(self
, other
):
172 raise NotImplementedError
173 self
.__check
_divisor
()
174 return Operator("%", [other
, self
])
176 def __floordiv__(self
, other
):
177 raise NotImplementedError
178 other
= Value
.cast(other
)
179 other
.__check
_divisor
()
180 return Operator("//", [self
, other
])
182 def __rfloordiv__(self
, other
):
183 raise NotImplementedError
184 self
.__check
_divisor
()
185 return Operator("//", [other
, self
])
187 # binary comparison ops that need partitioning
189 def _compare(self
, width
, op1
, op2
, opname
, optype
):
190 # print (opname, op1, op2)
191 pa
= PartitionedEqGtGe(width
, self
.partpoints
)
192 setattr(self
.m
.submodules
, self
.get_modname(opname
), pa
)
194 comb
+= pa
.opcode
.eq(optype
) # set opcode
195 if isinstance(op1
, PartitionedSignal
):
196 comb
+= pa
.a
.eq(op1
.sig
)
199 if isinstance(op2
, PartitionedSignal
):
200 comb
+= pa
.b
.eq(op2
.sig
)
205 def __eq__(self
, other
):
206 width
= self
.sig
.shape()[0]
207 return self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
209 def __ne__(self
, other
):
210 width
= self
.sig
.shape()[0]
211 eq
= self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
212 ne
= Signal(eq
.width
)
213 self
.m
.d
.comb
+= ne
.eq(~eq
)
216 def __gt__(self
, other
):
217 width
= self
.sig
.shape()[0]
218 return self
._compare
(width
, self
, other
, "gt", PartitionedEqGtGe
.GT
)
220 def __lt__(self
, other
):
221 width
= self
.sig
.shape()[0]
222 return self
._compare
(width
, other
, self
, "gt", PartitionedEqGtGe
.GT
)
224 def __ge__(self
, other
):
225 width
= self
.sig
.shape()[0]
226 return self
._compare
(width
, self
, other
, "ge", PartitionedEqGtGe
.GE
)
228 def __le__(self
, other
):
229 width
= self
.sig
.shape()[0]
230 return self
._compare
(width
, other
, self
, "ge", PartitionedEqGtGe
.GE
)
235 """Conversion to boolean.
240 ``1`` if any bits are set, ``0`` otherwise.
242 raise NotImplementedError
243 return Operator("b", [self
])
246 """Check if any bits are ``1``.
251 ``1`` if any bits are set, ``0`` otherwise.
253 raise NotImplementedError
254 return Operator("r|", [self
])
257 """Check if all bits are ``1``.
262 ``1`` if all bits are set, ``0`` otherwise.
264 raise NotImplementedError
265 return Operator("r&", [self
])
268 """Compute pairwise exclusive-or of every bit.
273 ``1`` if an odd number of bits are set, ``0`` if an
274 even number of bits are set.
276 raise NotImplementedError
277 return Operator("r^", [self
])
279 def implies(premise
, conclusion
):
285 ``0`` if ``premise`` is true and ``conclusion`` is not,
288 return ~premise | conclusion