1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
7 dynamic-partitionable class similar to Signal, which, when the partition
8 is fully open will be identical to Signal. when partitions are closed,
9 the class turns into a SIMD variant of Signal. *this is dynamic*.
11 the basic fundamental idea is: write code once, and if you want a SIMD
12 version of it, use PartitionedSignal in place of Signal. job done.
13 this however requires the code to *not* be designed to use nmigen.If,
14 nmigen.Case, or other constructs: only Mux and other logic.
16 http://bugs.libre-riscv.org/show_bug.cgi?id=132
19 from ieee754
.part_mul_add
.adder
import PartitionedAdder
20 #from ieee754.part_cmp.equal_ortree import PartitionedEq
21 from ieee754
.part_cmp
.eq_gt_ge
import PartitionedEqGtGe
22 from ieee754
.part_mul_add
.partpoints
import make_partition
23 from operator
import or_
, xor
, and_
, not_
25 from nmigen
import (Signal
,
27 def applyop(op1
, op2
, op
):
28 if isinstance(op1
, PartitionedSignal
):
30 if isinstance(op2
, PartitionedSignal
):
35 class PartitionedSignal
:
36 def __init__(self
, mask
, *args
, **kwargs
):
37 self
.sig
= Signal(*args
, **kwargs
)
38 width
= self
.sig
.shape()[0] # get signal width
39 self
.partpoints
= make_partition(mask
, width
) # create partition points
41 for name
in ['add', 'eq', 'gt', 'ge']:
42 self
.modnames
[name
] = 0
44 def set_module(self
, m
):
47 def get_modname(self
, category
):
48 self
.modnames
[category
] += 1
49 return "%s%d" % (category
, self
.modnames
[category
])
52 return self
.sig
.eq(val
)
54 # unary ops that require partitioning
57 return Operator("~", [self
])
59 return Operator("-", [self
])
61 # binary ops that don't require partitioning
63 def __and__(self
, other
):
64 return applyop(self
, other
, and_
)
66 def __rand__(self
, other
):
67 return applyop(other
, self
, and_
)
69 def __or__(self
, other
):
70 return applyop(self
, other
, or_
)
72 def __ror__(self
, other
):
73 return applyop(other
, self
, or_
)
75 def __xor__(self
, other
):
76 return applyop(self
, other
, xor
)
78 def __rxor__(self
, other
):
79 return applyop(other
, self
, xor
)
81 # binary ops that need partitioning
83 def __add__(self
, other
):
84 shape
= self
.sig
.shape()
85 pa
= PartitionedAdder(shape
[0], self
.partpoints
)
86 setattr(self
.m
.submodules
, self
.get_modname('add'), pa
)
88 comb
+= pa
.a
.eq(self
.sig
)
89 if isinstance(other
, PartitionedSignal
):
90 comb
+= pa
.b
.eq(other
.sig
)
92 comb
+= pa
.b
.eq(other
)
95 def __radd__(self
, other
):
96 return Operator("+", [other
, self
])
97 def __sub__(self
, other
):
98 return Operator("-", [self
, other
])
99 def __rsub__(self
, other
):
100 return Operator("-", [other
, self
])
102 def __mul__(self
, other
):
103 return Operator("*", [self
, other
])
104 def __rmul__(self
, other
):
105 return Operator("*", [other
, self
])
107 def __check_divisor(self
):
108 width
, signed
= self
.shape()
110 # Python's division semantics and Verilog's division semantics
111 # differ for negative divisors (Python uses div/mod, Verilog
112 # uses quo/rem); for now, avoid the issue
113 # completely by prohibiting such division operations.
114 raise NotImplementedError(
115 "Division by a signed value is not supported")
116 def __mod__(self
, other
):
117 other
= Value
.cast(other
)
118 other
.__check
_divisor
()
119 return Operator("%", [self
, other
])
120 def __rmod__(self
, other
):
121 self
.__check
_divisor
()
122 return Operator("%", [other
, self
])
123 def __floordiv__(self
, other
):
124 other
= Value
.cast(other
)
125 other
.__check
_divisor
()
126 return Operator("//", [self
, other
])
127 def __rfloordiv__(self
, other
):
128 self
.__check
_divisor
()
129 return Operator("//", [other
, self
])
131 def __lshift__(self
, other
):
132 return Operator("<<", [self
, other
])
133 def __rlshift__(self
, other
):
134 return Operator("<<", [other
, self
])
135 def __rshift__(self
, other
):
136 return Operator(">>", [self
, other
])
138 # binary comparison ops that need partitioning
140 def _compare(self
, width
, op1
, op2
, opname
, optype
):
141 #print (opname, op1, op2)
142 pa
= PartitionedEqGtGe(width
, self
.partpoints
)
143 setattr(self
.m
.submodules
, self
.get_modname(opname
), pa
)
145 comb
+= pa
.opcode
.eq(optype
) # set opcode
146 if isinstance(op1
, PartitionedSignal
):
147 comb
+= pa
.a
.eq(op1
.sig
)
150 if isinstance(op2
, PartitionedSignal
):
151 comb
+= pa
.b
.eq(op2
.sig
)
156 def __eq__(self
, other
):
157 width
= self
.sig
.shape()[0]
158 return self
._compare
(width
, self
, other
, "eq", PartitionedEqGtGe
.EQ
)
160 def __ne__(self
, other
):
161 width
= self
.sig
.shape()[0]
162 invert
= ~self
.sig
# invert the input before compare EQ. TODO: NE op
163 return self
._compare
(width
, invert
, other
, "eq", PartitionedEqGtGe
.EQ
)
165 def __gt__(self
, other
):
166 width
= self
.sig
.shape()[0]
167 return self
._compare
(width
, self
, other
, "gt", PartitionedEqGtGe
.GT
)
169 def __lt__(self
, other
):
170 width
= self
.sig
.shape()[0]
171 return self
._compare
(width
, other
, self
, "gt", PartitionedEqGtGe
.GT
)
173 def __ge__(self
, other
):
174 width
= self
.sig
.shape()[0]
175 return self
._compare
(width
, self
, other
, "ge", PartitionedEqGtGe
.GE
)
177 def __le__(self
, other
):
178 width
= self
.sig
.shape()[0]
179 return self
._compare
(width
, other
, self
, "ge", PartitionedEqGtGe
.GE
)