src/ieee754/part/partsig.py

   1 # SPDX-License-Identifier: LGPL-2.1-or-later
   2 # See Notices.txt for copyright information
   3
   4 """
   5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   6
   7 dynamic-partitionable class similar to Signal, which, when the partition
   8 is fully open will be identical to Signal.  when partitions are closed,
   9 the class turns into a SIMD variant of Signal.  *this is dynamic*.
  10
  11 the basic fundamental idea is: write code once, and if you want a SIMD
  12 version of it, use PartitionedSignal in place of Signal.  job done.
  13 this however requires the code to *not* be designed to use nmigen.If,
  14 nmigen.Case, or other constructs: only Mux and other logic.
  15
  16 * http://bugs.libre-riscv.org/show_bug.cgi?id=132
  17 """
  18
  19 from ieee754.part_mul_add.adder import PartitionedAdder
  20 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
  21 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
  22 from ieee754.part_mul_add.partpoints import make_partition
  23 from operator import or_, xor, and_, not_
  24
  25 from nmigen import (Signal)
  26
  27
  28 def getsig(op1):
  29     if isinstance(op1, PartitionedSignal):
  30         op1 = op1.sig
  31     return op1
  32
  33
  34 def applyop(op1, op2, op):
  35     return op(getsig(op1), getsig(op2))
  36
  37
  38 class PartitionedSignal:
  39     def __init__(self, mask, *args, **kwargs):
  40         self.sig = Signal(*args, **kwargs)
  41         width = self.sig.shape()[0]  # get signal width
  42         # create partition points
  43         self.partpoints = make_partition(mask, width)
  44         self.modnames = {}
  45         for name in ['add', 'eq', 'gt', 'ge', 'ls']:
  46             self.modnames[name] = 0
  47
  48     def set_module(self, m):
  49         self.m = m
  50
  51     def get_modname(self, category):
  52         self.modnames[category] += 1
  53         return "%s%d" % (category, self.modnames[category])
  54
  55     def eq(self, val):
  56         return self.sig.eq(getsig(val))
  57
  58     # unary ops that do not require partitioning
  59
  60     def __invert__(self):
  61         return ~self.sig
  62
  63     # unary ops that require partitioning
  64
  65     def __neg__(self):
  66         result, _ = self.add_op(self, ~0, carry=0)  # TODO, subop
  67         return result
  68
  69     # binary ops that don't require partitioning
  70
  71     def __and__(self, other):
  72         return applyop(self, other, and_)
  73
  74     def __rand__(self, other):
  75         return applyop(other, self, and_)
  76
  77     def __or__(self, other):
  78         return applyop(self, other, or_)
  79
  80     def __ror__(self, other):
  81         return applyop(other, self, or_)
  82
  83     def __xor__(self, other):
  84         return applyop(self, other, xor)
  85
  86     def __rxor__(self, other):
  87         return applyop(other, self, xor)
  88
  89     # binary ops that need partitioning
  90
  91     # TODO: detect if the 2nd operand is a Const, a Signal or a
  92     # PartitionedSignal.  if it's a Const or a Signal, a global shift
  93     # can occur.  if it's a PartitionedSignal, that's much more interesting.
  94     def ls_op(self, op1, op2, carry):
  95         op1 = getsig(op1)
  96         op2 = getsig(op2)
  97         shape = op1.shape()
  98         pa = PartitionedDynamicShift(shape[0], self.partpoints)
  99         setattr(self.m.submodules, self.get_modname('ls'), pa)
 100         comb = self.m.d.comb
 101         comb += pa.a.eq(op1)
 102         comb += pa.b.eq(op2)
 103         # XXX TODO: carry-in, carry-out
 104         #comb += pa.carry_in.eq(carry)
 105         return (pa.output, 0)
 106
 107     def __lshift__(self, other):
 108         result, _ = self.ls_op(self, other, carry=0)
 109         return result
 110
 111     def __rlshift__(self, other):
 112         raise NotImplementedError
 113         return Operator("<<", [other, self])
 114
 115     def __rshift__(self, other):
 116         raise NotImplementedError
 117         return Operator(">>", [self, other])
 118
 119     def __rrshift__(self, other):
 120         raise NotImplementedError
 121         return Operator(">>", [other, self])
 122
 123     def add_op(self, op1, op2, carry):
 124         op1 = getsig(op1)
 125         op2 = getsig(op2)
 126         shape = op1.shape()
 127         pa = PartitionedAdder(shape[0], self.partpoints)
 128         setattr(self.m.submodules, self.get_modname('add'), pa)
 129         comb = self.m.d.comb
 130         comb += pa.a.eq(op1)
 131         comb += pa.b.eq(op2)
 132         comb += pa.carry_in.eq(carry)
 133         return (pa.output, pa.carry_out)
 134
 135     def sub_op(self, op1, op2, carry=~0):
 136         op1 = getsig(op1)
 137         op2 = getsig(op2)
 138         shape = op1.shape()
 139         pa = PartitionedAdder(shape[0], self.partpoints)
 140         setattr(self.m.submodules, self.get_modname('add'), pa)
 141         comb = self.m.d.comb
 142         comb += pa.a.eq(op1)
 143         comb += pa.b.eq(~op2)
 144         comb += pa.carry_in.eq(carry)
 145         return (pa.output, pa.carry_out)
 146
 147     def __add__(self, other):
 148         result, _ = self.add_op(self, other, carry=0)
 149         return result
 150
 151     def __radd__(self, other):
 152         result, _ = self.add_op(other, self)
 153         return result
 154
 155     def __sub__(self, other):
 156         result, _ = self.sub_op(self, other)
 157         return result
 158
 159     def __rsub__(self, other):
 160         result, _ = self.sub_op(other, self)
 161         return result
 162
 163     def __mul__(self, other):
 164         return Operator("*", [self, other])
 165
 166     def __rmul__(self, other):
 167         return Operator("*", [other, self])
 168
 169     def __check_divisor(self):
 170         width, signed = self.shape()
 171         if signed:
 172             # Python's division semantics and Verilog's division semantics
 173             # differ for negative divisors (Python uses div/mod, Verilog
 174             # uses quo/rem); for now, avoid the issue
 175             # completely by prohibiting such division operations.
 176             raise NotImplementedError(
 177                     "Division by a signed value is not supported")
 178
 179     def __mod__(self, other):
 180         raise NotImplementedError
 181         other = Value.cast(other)
 182         other.__check_divisor()
 183         return Operator("%", [self, other])
 184
 185     def __rmod__(self, other):
 186         raise NotImplementedError
 187         self.__check_divisor()
 188         return Operator("%", [other, self])
 189
 190     def __floordiv__(self, other):
 191         raise NotImplementedError
 192         other = Value.cast(other)
 193         other.__check_divisor()
 194         return Operator("//", [self, other])
 195
 196     def __rfloordiv__(self, other):
 197         raise NotImplementedError
 198         self.__check_divisor()
 199         return Operator("//", [other, self])
 200
 201     # binary comparison ops that need partitioning
 202
 203     def _compare(self, width, op1, op2, opname, optype):
 204         # print (opname, op1, op2)
 205         pa = PartitionedEqGtGe(width, self.partpoints)
 206         setattr(self.m.submodules, self.get_modname(opname), pa)
 207         comb = self.m.d.comb
 208         comb += pa.opcode.eq(optype)  # set opcode
 209         if isinstance(op1, PartitionedSignal):
 210             comb += pa.a.eq(op1.sig)
 211         else:
 212             comb += pa.a.eq(op1)
 213         if isinstance(op2, PartitionedSignal):
 214             comb += pa.b.eq(op2.sig)
 215         else:
 216             comb += pa.b.eq(op2)
 217         return pa.output
 218
 219     def __eq__(self, other):
 220         width = self.sig.shape()[0]
 221         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 222
 223     def __ne__(self, other):
 224         width = self.sig.shape()[0]
 225         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 226         ne = Signal(eq.width)
 227         self.m.d.comb += ne.eq(~eq)
 228         return ne
 229
 230     def __gt__(self, other):
 231         width = self.sig.shape()[0]
 232         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 233
 234     def __lt__(self, other):
 235         width = self.sig.shape()[0]
 236         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 237
 238     def __ge__(self, other):
 239         width = self.sig.shape()[0]
 240         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 241
 242     def __le__(self, other):
 243         width = self.sig.shape()[0]
 244         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 245
 246     # useful operators
 247
 248     def bool(self):
 249         """Conversion to boolean.
 250
 251         Returns
 252         -------
 253         Value, out
 254             ``1`` if any bits are set, ``0`` otherwise.
 255         """
 256         raise NotImplementedError
 257         return Operator("b", [self])
 258
 259     def any(self):
 260         """Check if any bits are ``1``.
 261
 262         Returns
 263         -------
 264         Value, out
 265             ``1`` if any bits are set, ``0`` otherwise.
 266         """
 267         raise NotImplementedError
 268         return Operator("r|", [self])
 269
 270     def all(self):
 271         """Check if all bits are ``1``.
 272
 273         Returns
 274         -------
 275         Value, out
 276             ``1`` if all bits are set, ``0`` otherwise.
 277         """
 278         raise NotImplementedError
 279         return Operator("r&", [self])
 280
 281     def xor(self):
 282         """Compute pairwise exclusive-or of every bit.
 283
 284         Returns
 285         -------
 286         Value, out
 287             ``1`` if an odd number of bits are set, ``0`` if an
 288                   even number of bits are set.
 289         """
 290         # XXXX TODO: return partition-mask-sized set of bits
 291         raise NotImplementedError
 292         return Operator("r^", [self])
 293
 294     def implies(premise, conclusion):
 295         """Implication.
 296
 297         Returns
 298         -------
 299         Value, out
 300             ``0`` if ``premise`` is true and ``conclusion`` is not,
 301             ``1`` otherwise.
 302         """
 303         # amazingly, this should actually work.
 304         return ~premise | conclusion