src/ieee754/part/test/test_partsig.py

   1 #!/usr/bin/env python3
   2 # SPDX-License-Identifier: LGPL-2.1-or-later
   3 # See Notices.txt for copyright information
   4
   5 from nmigen import Signal, Module, Elaboratable
   6 from nmigen.back.pysim import Simulator, Delay, Tick, Passive
   7 from nmigen.cli import verilog, rtlil
   8
   9 from ieee754.part.partsig import PartitionedSignal
  10 from ieee754.part_mux.part_mux import PMux
  11
  12 from random import randint
  13 import unittest
  14 import itertools
  15
  16
  17 def perms(k):
  18     return map(''.join, itertools.product('01', repeat=k))
  19
  20
  21 def create_ilang(dut, traces, test_name):
  22     vl = rtlil.convert(dut, ports=traces)
  23     with open("%s.il" % test_name, "w") as f:
  24         f.write(vl)
  25
  26
  27 def create_simulator(module, traces, test_name):
  28     create_ilang(module, traces, test_name)
  29     return Simulator(module,
  30                      vcd_file=open(test_name + ".vcd", "w"),
  31                      gtkw_file=open(test_name + ".gtkw", "w"),
  32                      traces=traces)
  33
  34 class TestAddMod(Elaboratable):
  35     def __init__(self, width, partpoints):
  36         self.partpoints = partpoints
  37         self.a = PartitionedSignal(partpoints, width)
  38         self.b = PartitionedSignal(partpoints, width)
  39         self.add_output = Signal(width)
  40         self.eq_output = Signal(len(partpoints)+1)
  41         self.gt_output = Signal(len(partpoints)+1)
  42         self.ge_output = Signal(len(partpoints)+1)
  43         self.ne_output = Signal(len(partpoints)+1)
  44         self.lt_output = Signal(len(partpoints)+1)
  45         self.le_output = Signal(len(partpoints)+1)
  46         self.mux_sel = Signal(len(partpoints)+1)
  47         self.mux_out = Signal(width)
  48         self.carry_in = Signal(len(partpoints)+1)
  49         self.add_carry_out = Signal(len(partpoints)+1)
  50         self.sub_carry_out = Signal(len(partpoints)+1)
  51
  52     def elaborate(self, platform):
  53         m = Module()
  54         self.a.set_module(m)
  55         self.b.set_module(m)
  56         m.d.comb += self.lt_output.eq(self.a < self.b)
  57         m.d.comb += self.ne_output.eq(self.a != self.b)
  58         m.d.comb += self.le_output.eq(self.a <= self.b)
  59         m.d.comb += self.gt_output.eq(self.a > self.b)
  60         m.d.comb += self.eq_output.eq(self.a == self.b)
  61         m.d.comb += self.ge_output.eq(self.a >= self.b)
  62         # add
  63         add_out, add_carry = self.a.add_op(self.a, self.b,
  64                                            self.carry_in)
  65         m.d.comb += self.add_output.eq(add_out)
  66         m.d.comb += self.add_carry_out.eq(add_carry)
  67         if hasattr(self.a, "sub_op"): # TODO, remove this
  68             # sub
  69             sub_out, sub_carry = self.a.sub_op(self.a, self.b,
  70                                                self.carry_in)
  71             m.d.comb += self.sub_output.eq(sub_out)
  72             m.d.comb += self.sub_carry_out.eq(add_carry)
  73         ppts = self.partpoints
  74         m.d.comb += self.mux_out.eq(PMux(m, ppts, self.mux_sel, self.a, self.b))
  75
  76         return m
  77
  78
  79 class TestPartitionPoints(unittest.TestCase):
  80     def test(self):
  81         width = 16
  82         part_mask = Signal(4) # divide into 4-bits
  83         module = TestAddMod(width, part_mask)
  84
  85         sim = create_simulator(module,
  86                               [part_mask,
  87                                module.a.sig,
  88                                module.b.sig,
  89                                module.add_output,
  90                                module.eq_output],
  91                               "part_sig_add")
  92         def async_process():
  93
  94             def test_add_fn(carry_in, a, b, mask):
  95                 lsb = mask & ~(mask-1) if carry_in else 0
  96                 return mask & ((a & mask) + (b & mask) + lsb)
  97
  98             def test_sub_fn(carry_in, a, b, mask):
  99                 raise NotImplementedError
 100                 # TODO
 101                 lsb = mask & ~(mask-1) if carry_in else 0
 102                 return mask & ((a & mask) + (b & mask) + lsb)
 103
 104             def test_op(msg_prefix, carry, test_fn, mod_attr, *mask_list):
 105                 rand_data = []
 106                 for i in range(100):
 107                     a, b = randint(0, 1<<16), randint(0, 1<<16)
 108                     rand_data.append((a, b))
 109                 for a, b in [(0x0000, 0x0000),
 110                              (0x1234, 0x1234),
 111                              (0xABCD, 0xABCD),
 112                              (0xFFFF, 0x0000),
 113                              (0x0000, 0x0000),
 114                              (0xFFFF, 0xFFFF),
 115                              (0x0000, 0xFFFF)] + rand_data:
 116                     yield module.a.eq(a)
 117                     yield module.b.eq(b)
 118                     carry_sig = 0xf if carry else 0
 119                     yield module.carry_in.eq(carry_sig)
 120                     yield Delay(0.1e-6)
 121                     y = 0
 122                     for i, mask in enumerate(mask_list):
 123                         y |= test_fn(carry, a, b, mask)
 124                     outval = (yield getattr(module, "%s_output" % mod_attr))
 125                     # TODO: get (and test) carry output as well
 126                     print(a, b, outval, carry)
 127                     msg = f"{msg_prefix}: 0x{a:X} + 0x{b:X}" + \
 128                         f" => 0x{y:X} != 0x{outval:X}"
 129                     self.assertEqual(y, outval, msg)
 130
 131             for (test_fn, mod_attr) in ((test_add_fn, "add"),
 132                                         #(test_sub_fn, "sub"),
 133                                         ):
 134                 yield part_mask.eq(0)
 135                 yield from test_op("16-bit", 1, test_fn, mod_attr, 0xFFFF)
 136                 yield from test_op("16-bit", 0, test_fn, mod_attr, 0xFFFF)
 137                 yield part_mask.eq(0b10)
 138                 yield from test_op("8-bit", 0, test_fn, mod_attr,
 139                                                0xFF00, 0x00FF)
 140                 yield from test_op("8-bit", 1, test_fn, mod_attr,
 141                                                0xFF00, 0x00FF)
 142                 yield part_mask.eq(0b1111)
 143                 yield from test_op("4-bit", 0, test_fn, mod_attr,
 144                                                0xF000, 0x0F00, 0x00F0, 0x000F)
 145                 yield from test_op("4-bit", 1, test_fn, mod_attr,
 146                                                0xF000, 0x0F00, 0x00F0, 0x000F)
 147
 148             def test_ne_fn(a, b, mask):
 149                 return (a & mask) != (b & mask)
 150
 151             def test_lt_fn(a, b, mask):
 152                 return (a & mask) < (b & mask)
 153
 154             def test_le_fn(a, b, mask):
 155                 return (a & mask) <= (b & mask)
 156
 157             def test_eq_fn(a, b, mask):
 158                 return (a & mask) == (b & mask)
 159
 160             def test_gt_fn(a, b, mask):
 161                 return (a & mask) > (b & mask)
 162
 163             def test_ge_fn(a, b, mask):
 164                 return (a & mask) >= (b & mask)
 165
 166             def test_binop(msg_prefix, test_fn, mod_attr, *maskbit_list):
 167                 for a, b in [(0x0000, 0x0000),
 168                              (0x1234, 0x1234),
 169                              (0xABCD, 0xABCD),
 170                              (0xFFFF, 0x0000),
 171                              (0x0000, 0x0000),
 172                              (0xFFFF, 0xFFFF),
 173                              (0x0000, 0xFFFF),
 174                              (0xABCD, 0xABCE),
 175                              (0x8000, 0x0000),
 176                              (0xBEEF, 0xFEED)]:
 177                     yield module.a.eq(a)
 178                     yield module.b.eq(b)
 179                     yield Delay(0.1e-6)
 180                     # convert to mask_list
 181                     mask_list = []
 182                     for mb in maskbit_list:
 183                         v = 0
 184                         for i in range(4):
 185                             if mb & (1<<i):
 186                                 v |= 0xf << (i*4)
 187                         mask_list.append(v)
 188                     y = 0
 189                     # do the partitioned tests
 190                     for i, mask in enumerate(mask_list):
 191                         if test_fn(a, b, mask):
 192                             # OR y with the lowest set bit in the mask
 193                             y |= maskbit_list[i]
 194                     # check the result
 195                     outval = (yield getattr(module, "%s_output" % mod_attr))
 196                     msg = f"{msg_prefix}: {mod_attr} 0x{a:X} == 0x{b:X}" + \
 197                         f" => 0x{y:X} != 0x{outval:X}, masklist %s"
 198                     print ((msg % str(maskbit_list)).format(locals()))
 199                     self.assertEqual(y, outval, msg % str(maskbit_list))
 200
 201             for (test_fn, mod_attr) in ((test_eq_fn, "eq"),
 202                                         (test_gt_fn, "gt"),
 203                                         (test_ge_fn, "ge"),
 204                                         (test_lt_fn, "lt"),
 205                                         (test_le_fn, "le"),
 206                                         (test_ne_fn, "ne"),
 207                                         ):
 208                 yield part_mask.eq(0)
 209                 yield from test_binop("16-bit", test_fn, mod_attr, 0b1111)
 210                 yield part_mask.eq(0b10)
 211                 yield from test_binop("8-bit", test_fn, mod_attr,
 212                                       0b1100, 0b0011)
 213                 yield part_mask.eq(0b1111)
 214                 yield from test_binop("4-bit", test_fn, mod_attr,
 215                                       0b1000, 0b0100, 0b0010, 0b0001)
 216
 217             def test_muxop(msg_prefix, *maskbit_list):
 218                 for a, b in [(0x0000, 0x0000),
 219                              (0x1234, 0x1234),
 220                              (0xABCD, 0xABCD),
 221                              (0xFFFF, 0x0000),
 222                              (0x0000, 0x0000),
 223                              (0xFFFF, 0xFFFF),
 224                              (0x0000, 0xFFFF)]:
 225                     # convert to mask_list
 226                     mask_list = []
 227                     for mb in maskbit_list:
 228                         v = 0
 229                         for i in range(4):
 230                             if mb & (1<<i):
 231                                 v |= 0xf << (i*4)
 232                         mask_list.append(v)
 233
 234                     # TODO: sel needs to go through permutations of mask_list
 235                     for p in perms(len(mask_list)):
 236
 237                         sel = 0
 238                         selmask = 0
 239                         for i, v in enumerate(p):
 240                             if v == '1':
 241                                 sel |= maskbit_list[i]
 242                                 selmask |= mask_list[i]
 243
 244                         yield module.a.eq(a)
 245                         yield module.b.eq(b)
 246                         yield module.mux_sel.eq(sel)
 247                         yield Delay(0.1e-6)
 248                         y = 0
 249                         # do the partitioned tests
 250                         for i, mask in enumerate(mask_list):
 251                             if (selmask & mask):
 252                                 y |= (a & mask)
 253                             else:
 254                                 y |= (b & mask)
 255                         # check the result
 256                         outval = (yield module.mux_out)
 257                         msg = f"{msg_prefix}: mux " + \
 258                             f"0x{sel:X} ? 0x{a:X} : 0x{b:X}" + \
 259                             f" => 0x{y:X} != 0x{outval:X}, masklist %s"
 260                         #print ((msg % str(maskbit_list)).format(locals()))
 261                         self.assertEqual(y, outval, msg % str(maskbit_list))
 262
 263             yield part_mask.eq(0)
 264             yield from test_muxop("16-bit", 0b1111)
 265             yield part_mask.eq(0b10)
 266             yield from test_muxop("8-bit", 0b1100, 0b0011)
 267             yield part_mask.eq(0b1111)
 268             yield from test_muxop("4-bit", 0b1000, 0b0100, 0b0010, 0b0001)
 269
 270         sim.add_process(async_process)
 271         sim.run()
 272
 273 if __name__ == '__main__':
 274     unittest.main()
 275