c5471f51020aab84e5c3502dc9eeb76e886ee3d1
[ieee754fpu.git] / src / ieee754 / part_bits / xor.py
1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
3
4 """
5 Copyright (C) 2020 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6
7 dynamically-partitionable "xor" class, directly equivalent
8 to Signal.xor() except SIMD-partitionable
9
10 See:
11
12 * http://libre-riscv.org/3d_gpu/architecture/dynamic_simd/logicops
13 * http://bugs.libre-riscv.org/show_bug.cgi?id=176
14 """
15
16 from nmigen import Signal, Module, Elaboratable, Cat, C, Mux, Repl
17 from nmigen.cli import main
18
19 from ieee754.part_mul_add.partpoints import PartitionPoints
20 from ieee754.part_cmp.experiments.eq_combiner import XORCombiner
21
22
23 class PartitionedXOR(Elaboratable):
24
25 def __init__(self, width, partition_points):
26 """Create a ``PartitionedXOR`` operator
27 """
28 self.width = width
29 self.a = Signal(width, reset_less=True)
30 self.partition_points = PartitionPoints(partition_points)
31 self.mwidth = len(self.partition_points)+1
32 self.output = Signal(self.mwidth, reset_less=True)
33 if not self.partition_points.fits_in_width(width):
34 raise ValueError("partition_points doesn't fit in width")
35
36 def elaborate(self, platform):
37 m = Module()
38 comb = m.d.comb
39 m.submodules.xorc = xorc = XORCombiner(self.mwidth)
40
41 # make a series of "xor", splitting a and b into partition chunks
42 xors = Signal(self.mwidth, reset_less=True)
43 xorl = []
44 keys = list(self.partition_points.keys()) + [self.width]
45 start = 0
46 for i in range(len(keys)):
47 end = keys[i]
48 xorl.append(self.a[start:end].xor())
49 start = end # for next time round loop
50 comb += xors.eq(Cat(*xorl))
51
52 # put the partial results through the combiner
53 comb += xorc.gates.eq(self.partition_points.as_sig())
54 comb += xorc.neqs.eq(xors)
55 comb += self.output.eq(xorc.outputs)
56
57 return m