simplify sign/term bits using Cat
[ieee754fpu.git] / src / ieee754 / part_mul_add / multiply.pyi
1 # SPDX-License-Identifier: LGPL-2.1-or-later
2 # See Notices.txt for copyright information
3 """Integer Multiplication."""
4
5 from typing import Any, NewType, Union, List, Dict, Iterable, Mapping, Optional
6 from typing_extensions import final
7
8 PartitionPointsIn = Mapping[int, Union[Value, bool, int]]
9
10 class PartitionPoints(Dict[int, Value]):
11 def __init__(self, partition_points: Optional[PartitionPointsIn] = None):
12 ...
13
14 def like(self,
15 name: Optional[str] = None,
16 src_loc_at: int = 0) -> 'PartitionPoints':
17 ...
18
19 def eq(self, rhs: 'PartitionPoints') -> Iterable[Assign]:
20 ...
21
22 def as_mask(self, width: int) -> Value:
23 bits: List[Union[Value, bool]]
24
25 def get_max_partition_count(self, width: int) -> int:
26 ...
27
28 def fits_in_width(self, width: int) -> bool:
29 ...
30
31
32 @final
33 class FullAdder(Elaboratable):
34 def __init__(self, width: int):
35 ...
36
37 def elaborate(self, platform: Any) -> Module:
38 ...
39
40
41 @final
42 class PartitionedAdder(Elaboratable):
43 def __init__(self, width: int, partition_points: PartitionPointsIn):
44 ...
45
46 def elaborate(self, platform: Any) -> Module:
47 ...
48
49
50 @final
51 class AddReduce(Elaboratable):
52 def __init__(self,
53 ...
54
55 @staticmethod
56 def get_max_level(input_count: int) -> int:
57 ...
58
59 def next_register_levels(self) -> Iterable[int]:
60 ...
61
62 @staticmethod
63 def full_adder_groups(input_count: int) -> range:
64 ...
65
66 def elaborate(self, platform: Any) -> Module:
67 intermediate_terms: List[Signal]
68 def add_intermediate_term(value: Value) -> None:
69 ...
70
71
72 class Mul8_16_32_64(Elaboratable):
73 def __init__(self, register_levels: Iterable[int] = ()):
74 ...
75
76 def _part_byte(self, index: int) -> Value:
77 ...
78
79 def elaborate(self, platform: Any) -> Module:
80 ...
81
82 def add_term(value: Value,
83 shift: int = 0,
84 enabled: Optional[Value] = None) -> None:
85 ...