src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 #from nmutil.latch import SRLatch
   6 from dependence_cell import DependenceCell
   7 from fu_wr_pending import FU_RW_Pend
   8 from reg_select import Reg_Rsv
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col):
  32         self.n_fu_row = n_fu_row                  # Y (FUs)   ^v
  33         self.n_reg_col = n_reg_col                # X (Regs)  <>
  34         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  35         self.src1_i = Signal(n_reg_col, reset_less=True)     # oper1 in (top)
  36         self.src2_i = Signal(n_reg_col, reset_less=True)     # oper2 in (top)
  37         self.issue_i = Signal(n_reg_col, reset_less=True)    # Issue in (top)
  38
  39         self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  40         self.go_read_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  41
  42         # for Register File Select Lines (horizontal), per-reg
  43         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  44         self.src1_rsel_o = Signal(n_reg_col, reset_less=True) # src1 reg (bot)
  45         self.src2_rsel_o = Signal(n_reg_col, reset_less=True) # src2 reg (bot)
  46
  47         # for Function Unit "forward progress" (vertical), per-FU
  48         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  49         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  50
  51     def elaborate(self, platform):
  52         m = Module()
  53
  54         # ---
  55         # matrix of dependency cells
  56         # ---
  57         dm = Array(Array(DependenceCell() for r in range(self.n_fu_row)) \
  58                                           for f in range(self.n_reg_col))
  59         for rn in range(self.n_reg_col):
  60             for fu in range(self.n_fu_row):
  61                 setattr(m.submodules, "dm_r%d_fu%d" % (rn, fu), dm[rn][fu])
  62
  63         # ---
  64         # array of Function Unit Pending vectors
  65         # ---
  66         fupend = Array(FU_RW_Pend(self.n_reg_col) for f in range(self.n_fu_row))
  67         for fu in range(self.n_fu_row):
  68             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  69
  70         # ---
  71         # array of Register Reservation vectors
  72         # ---
  73         regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
  74         for rn in range(self.n_reg_col):
  75             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  76
  77         # ---
  78         # connect Function Unit vector
  79         # ---
  80         wr_pend = []
  81         rd_pend = []
  82         for fu in range(self.n_fu_row):
  83             fup = fupend[fu]
  84             dest_fwd_o = []
  85             src1_fwd_o = []
  86             src2_fwd_o = []
  87             for rn in range(self.n_reg_col):
  88                 dc = dm[rn][fu]
  89                 # accumulate cell fwd outputs for dest/src1/src2
  90                 dest_fwd_o.append(dc.dest_fwd_o)
  91                 src1_fwd_o.append(dc.src1_fwd_o)
  92                 src2_fwd_o.append(dc.src2_fwd_o)
  93             # connect cell fwd outputs to FU Vector in [Cat is gooood]
  94             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
  95                          fup.src1_fwd_i.eq(Cat(*src1_fwd_o)),
  96                          fup.src2_fwd_i.eq(Cat(*src2_fwd_o))
  97                         ]
  98             # accumulate FU Vector outputs
  99             wr_pend.append(fup.reg_wr_pend_o)
 100             rd_pend.append(fup.reg_rd_pend_o)
 101
 102         # ... and output them from this module (vertical, width=FUs)
 103         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 104         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 105
 106         # ---
 107         # connect Reg Selection vector
 108         # ---
 109         dest_rsel = []
 110         src1_rsel = []
 111         src2_rsel = []
 112         for rn in range(self.n_reg_col):
 113             rsv = regrsv[rn]
 114             dest_rsel_o = []
 115             src1_rsel_o = []
 116             src2_rsel_o = []
 117             for fu in range(self.n_fu_row):
 118                 dc = dm[rn][fu]
 119                 # accumulate cell reg-select outputs dest/src1/src2
 120                 dest_rsel_o.append(dc.dest_rsel_o)
 121                 src1_rsel_o.append(dc.src1_rsel_o)
 122                 src2_rsel_o.append(dc.src2_rsel_o)
 123             # connect cell reg-select outputs to Reg Vector In
 124             m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 125                          rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
 126                          rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
 127                         ]
 128             # accumulate Reg-Sel Vector outputs
 129             dest_rsel.append(rsv.dest_rsel_o)
 130             src1_rsel.append(rsv.src1_rsel_o)
 131             src2_rsel.append(rsv.src2_rsel_o)
 132
 133         # ... and output them from this module (horizontal, width=REGs)
 134         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 135         m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
 136         m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
 137
 138         # ---
 139         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 140         # ---
 141         for rn in range(self.n_reg_col):
 142             rsv = regrsv[rn]
 143             dest_i = []
 144             src1_i = []
 145             src2_i = []
 146             issue_i = []
 147             for fu in range(self.n_fu_row):
 148                 dc = dm[rn][fu]
 149                 # accumulate cell inputs dest/src1/src2
 150                 dest_i.append(dc.dest_i)
 151                 src1_i.append(dc.src1_i)
 152                 src2_i.append(dc.src2_i)
 153                 issue_i.append(dc.issue_i)
 154             # wire up inputs from module to row cell inputs (Cat is gooood)
 155             m.d.comb += [Cat(*dest_i).eq(self.dest_i),
 156                          Cat(*src1_i).eq(self.src1_i),
 157                          Cat(*src2_i).eq(self.src2_i),
 158                          Cat(*issue_i).eq(self.issue_i),
 159                         ]
 160
 161         # ---
 162         # connect Dependency Matrix go_read_i/go_write_i to module gr/gw
 163         # ---
 164         for fu in range(self.n_fu_row):
 165             fup = fupend[fu]
 166             go_read_i = []
 167             go_write_i = []
 168             for rn in range(self.n_reg_col):
 169                 dc = dm[rn][fu]
 170                 # accumulate cell fwd outputs for dest/src1/src2
 171                 go_read_i.append(dc.go_read_i)
 172                 go_write_i.append(dc.go_write_i)
 173             # wire up inputs from module to row cell inputs (Cat is gooood)
 174             m.d.comb += [Cat(*go_read_i).eq(self.go_read_i),
 175                          Cat(*go_write_i).eq(self.go_write_i),
 176                         ]
 177
 178         return m
 179
 180     def __iter__(self):
 181         yield self.dest_i
 182         yield self.src1_i
 183         yield self.src2_i
 184         yield self.issue_i
 185         yield self.go_write_i
 186         yield self.go_read_i
 187         yield self.dest_rsel_o
 188         yield self.src1_rsel_o
 189         yield self.src2_rsel_o
 190         yield self.wr_pend_o
 191         yield self.rd_pend_o
 192
 193     def ports(self):
 194         return list(self)
 195
 196 def d_matrix_sim(dut):
 197     """ XXX TODO
 198     """
 199     yield dut.dest_i.eq(1)
 200     yield dut.issue_i.eq(1)
 201     yield
 202     yield dut.issue_i.eq(0)
 203     yield
 204     yield dut.src1_i.eq(1)
 205     yield dut.issue_i.eq(1)
 206     yield
 207     yield dut.issue_i.eq(0)
 208     yield
 209     yield dut.go_read_i.eq(1)
 210     yield
 211     yield dut.go_read_i.eq(0)
 212     yield
 213     yield dut.go_write_i.eq(1)
 214     yield
 215     yield dut.go_write_i.eq(0)
 216     yield
 217
 218 def test_d_matrix():
 219     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4)
 220     vl = rtlil.convert(dut, ports=dut.ports())
 221     with open("test_fu_reg_matrix.il", "w") as f:
 222         f.write(vl)
 223
 224     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 225
 226 if __name__ == '__main__':
 227     test_d_matrix()