Expand FSGNJ module to 16 and 64 bit floats

[ieee754fpu.git] / src / ieee754 / fsgnj / fsgnj.py

diff --git a/src/ieee754/fsgnj/fsgnj.py b/src/ieee754/fsgnj/fsgnj.py
index 662181912ff3d2738857cc3d6d8821228619521a..c43e180c0c55d6e12ee081a5b6e236aad6a1e554 100644 (file)
--- a/src/ieee754/fsgnj/fsgnj.py
+++ b/src/ieee754/fsgnj/fsgnj.py
@@ -28,6 +28,8 @@ class FSGNJPipeMod(PipeModBase):
 
     def elaborate(self, platform):
         m = Module()
+
+        width = self.pspec.width
         comb = m.d.comb
 
         z1 = self.o.z
@@ -40,13 +42,15 @@ class FSGNJPipeMod(PipeModBase):
 
         with m.Switch(opcode):
             with m.Case(0b00):
-                comb += sign.eq(b[31])
+                comb += sign.eq(b[-1])
             with m.Case(0b01):
-                comb += sign.eq(~b[31])
+                comb += sign.eq(~b[-1])
             with m.Case(0b10):
-                comb += sign.eq(a[31] ^ b[31])
+                comb += sign.eq(a[-1] ^ b[-1])
+            with m.Default():
+                comb += sign.eq(b[-1])
 
-        comb += z1.eq(Cat(a[0:31], sign))
+        comb += z1.eq(Cat(a[0:width-1], sign))
 
         # copy the context (muxid, operator)
         comb += self.o.ctx.eq(self.i.ctx)