Reverse order of operations in implies()

[ieee754fpu.git] / src / ieee754 / part / partsig.py

diff --git a/src/ieee754/part/partsig.py b/src/ieee754/part/partsig.py
index 728764e77f972d75ba0229f4d5e2e821a059ea78..ab14bf9909fff362e132fab4b676bb228d9fd121 100644 (file)
--- a/src/ieee754/part/partsig.py
+++ b/src/ieee754/part/partsig.py
@@ -18,6 +18,7 @@ nmigen.Case, or other constructs: only Mux and other logic.
 
 from ieee754.part_mul_add.adder import PartitionedAdder
 from ieee754.part_cmp.eq_gt_ge import PartitionedEqGtGe
+from ieee754.part_bits.xor import PartitionedXOR
 from ieee754.part_shift.part_shift_dynamic import PartitionedDynamicShift
 from ieee754.part_shift.part_shift_scalar import PartitionedScalarShift
 from ieee754.part_mul_add.partpoints import make_partition, PartitionPoints
@@ -39,14 +40,14 @@ def applyop(op1, op2, op):
 class PartitionedSignal:
     def __init__(self, mask, *args, **kwargs):
         self.sig = Signal(*args, **kwargs)
-        width = self.sig.shape()[0]  # get signal width
+        width = len(self.sig)  # get signal width
         # create partition points
         if isinstance(mask, PartitionPoints):
             self.partpoints = mask
         else:
             self.partpoints = make_partition(mask, width)
         self.modnames = {}
-        for name in ['add', 'eq', 'gt', 'ge', 'ls']:
+        for name in ['add', 'eq', 'gt', 'ge', 'ls', 'xor']:
             self.modnames[name] = 0
 
     def set_module(self, m):
@@ -67,8 +68,8 @@ class PartitionedSignal:
     # unary ops that require partitioning
 
     def __neg__(self):
-        z = Const(0, len(self.partpoints)+1)
-        result, _ = self.add_op(self, ~0, carry=z)  # TODO, subop
+        z = Const(0, len(self.sig))
+        result, _ = self.sub_op(z, self)
         return result
 
     # binary ops that don't require partitioning
@@ -100,13 +101,11 @@ class PartitionedSignal:
         op1 = getsig(op1)
         if isinstance(op2, Const) or isinstance(op2, Signal):
             scalar = True
-            shape = op1.shape()
-            pa = PartitionedScalarShift(shape[0], self.partpoints)
+            pa = PartitionedScalarShift(len(op1), self.partpoints)
         else:
             scalar = False
             op2 = getsig(op2)
-            shape = op1.shape()
-            pa = PartitionedDynamicShift(shape[0], self.partpoints)
+            pa = PartitionedDynamicShift(len(op1), self.partpoints)
         setattr(self.m.submodules, self.get_modname('ls'), pa)
         comb = self.m.d.comb
         if scalar:
@@ -142,8 +141,7 @@ class PartitionedSignal:
     def add_op(self, op1, op2, carry):
         op1 = getsig(op1)
         op2 = getsig(op2)
-        shape = op1.shape()
-        pa = PartitionedAdder(shape[0], self.partpoints)
+        pa = PartitionedAdder(len(op1), self.partpoints)
         setattr(self.m.submodules, self.get_modname('add'), pa)
         comb = self.m.d.comb
         comb += pa.a.eq(op1)
@@ -154,8 +152,7 @@ class PartitionedSignal:
     def sub_op(self, op1, op2, carry=~0):
         op1 = getsig(op1)
         op2 = getsig(op2)
-        shape = op1.shape()
-        pa = PartitionedAdder(shape[0], self.partpoints)
+        pa = PartitionedAdder(len(op1), self.partpoints)
         setattr(self.m.submodules, self.get_modname('add'), pa)
         comb = self.m.d.comb
         comb += pa.a.eq(op1)
@@ -236,31 +233,31 @@ class PartitionedSignal:
         return pa.output
 
     def __eq__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         return self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
 
     def __ne__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         eq = self._compare(width, self, other, "eq", PartitionedEqGtGe.EQ)
         ne = Signal(eq.width)
         self.m.d.comb += ne.eq(~eq)
         return ne
 
     def __gt__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         return self._compare(width, self, other, "gt", PartitionedEqGtGe.GT)
 
     def __lt__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         # swap operands, use gt to do lt
         return self._compare(width, other, self, "gt", PartitionedEqGtGe.GT)
 
     def __ge__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         return self._compare(width, self, other, "ge", PartitionedEqGtGe.GE)
 
     def __le__(self, other):
-        width = self.sig.shape()[0]
+        width = len(self.sig)
         # swap operands, use ge to do le
         return self._compare(width, other, self, "ge", PartitionedEqGtGe.GE)
 
@@ -274,8 +271,8 @@ class PartitionedSignal:
         Value, out
             ``1`` if any bits are set, ``0`` otherwise.
         """
-        raise NotImplementedError
-        return Operator("b", [self])
+        return self.any() # have to see how this goes
+        #return Operator("b", [self])
 
     def any(self):
         """Check if any bits are ``1``.
@@ -285,7 +282,7 @@ class PartitionedSignal:
         Value, out
             ``1`` if any bits are set, ``0`` otherwise.
         """
-        raise NotImplementedError
+        return self != Const(0) # leverage the __ne__ operator here
         return Operator("r|", [self])
 
     def all(self):
@@ -296,8 +293,7 @@ class PartitionedSignal:
         Value, out
             ``1`` if all bits are set, ``0`` otherwise.
         """
-        raise NotImplementedError
-        return Operator("r&", [self])
+        return self == Const(-1) # leverage the __eq__ operator here
 
     def xor(self):
         """Compute pairwise exclusive-or of every bit.
@@ -308,9 +304,11 @@ class PartitionedSignal:
             ``1`` if an odd number of bits are set, ``0`` if an
                   even number of bits are set.
         """
-        # XXXX TODO: return partition-mask-sized set of bits
-        raise NotImplementedError
-        return Operator("r^", [self])
+        width = len(self.sig)
+        pa = PartitionedXOR(width, self.partpoints)
+        setattr(self.m.submodules, self.get_modname("xor"), pa)
+        self.m.d.comb += pa.a.eq(self.sig)
+        return pa.output
 
     def implies(premise, conclusion):
         """Implication.
@@ -322,4 +320,4 @@ class PartitionedSignal:
             ``1`` otherwise.
         """
         # amazingly, this should actually work.
-        return ~premise | conclusion
+        return conclusion | ~premise