Convert add and sub to return PartitionedSignal

[ieee754fpu.git] / src / ieee754 / part / test / test_partsig.py

diff --git a/src/ieee754/part/test/test_partsig.py b/src/ieee754/part/test/test_partsig.py
index 7d87eceebac77801362179bdb4a8ca50140ded55..2bf0ef837a7a6b5be5d26a645590962732b47577 100644 (file)
--- a/src/ieee754/part/test/test_partsig.py
+++ b/src/ieee754/part/test/test_partsig.py
@@ -149,15 +149,15 @@ class TestAddMod(Elaboratable):
         # add
         add_out, add_carry = self.a.add_op(self.a, self.b,
                                            self.carry_in)
-        comb += self.add_output.eq(add_out)
+        comb += self.add_output.eq(add_out.sig)
         comb += self.add_carry_out.eq(add_carry)
         # sub
         sub_out, sub_carry = self.a.sub_op(self.a, self.b,
                                            self.carry_in)
-        comb += self.sub_output.eq(sub_out)
+        comb += self.sub_output.eq(sub_out.sig)
         comb += self.sub_carry_out.eq(sub_carry)
         # neg
-        comb += self.neg_output.eq(-self.a)
+        comb += self.neg_output.eq((-self.a).sig)
         # left shift
         comb += self.ls_output.eq(self.a << self.b)
         # right shift