use bool() function instead of reduce(or_)

diff --git a/src/add/fpbase.py b/src/add/fpbase.py
index 0e4cd7a8ddfa5fcdf2e8a4131ce9a6c549667fff..d73183f3ec8b712fcab5b51954c2822326a9bf0d 100644 (file)
--- a/src/add/fpbase.py
+++ b/src/add/fpbase.py
@@ -327,7 +327,8 @@ class FPNumIn(FPNumBase):
         maxsleni = mw - maxslen
         m_mask = sm.rshift(self.m1s[1:], maxsleni) # shift and invert
 
-        stickybits = reduce(or_, inp.m[1:] & m_mask) | inp.m[0]
+        #stickybits = reduce(or_, inp.m[1:] & m_mask) | inp.m[0]
+        stickybits = (inp.m[1:] & m_mask).bool() | inp.m[0]
         return [self.e.eq(inp.e + diff),
                 self.m.eq(Cat(stickybits, rs))
                ]

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index e9464ce23f7407965023ae094ad673f423efe75b..af91721d047db2aa5fd83b7321f014258011133b 100644 (file)
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -867,7 +867,7 @@ class FPADD:
 
 
 if __name__ == "__main__":
-    alu = FPADD(width=32)
+    alu = FPADD(width=32, single_cycle=True)
     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())