enable single-cycle in FP16 test

diff --git a/src/add/test_add16.py b/src/add/test_add16.py
index 41b35f68612e323f1a08d0ff07ce45a90c208aab..f39ae8ae948c6a49d60686c1d3c01d2276f31122 100644 (file)
--- a/src/add/test_add16.py
+++ b/src/add/test_add16.py
@@ -39,6 +39,6 @@ def testbench(dut):
     yield from run_edge_cases(dut, count, add)
 
 if __name__ == '__main__':
-    dut = FPADD(width=16, single_cycle=False)
+    dut = FPADD(width=16, single_cycle=True)
     run_simulation(dut, testbench(dut), vcd_name="test_add16.vcd")