reduce next_bits by 1

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index 7c6fb181111544c2e85d763dc5764d21a7f232ca..133216986d9d16ea76b966a044a075a8fc8f1d3d 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -416,7 +416,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
         # compare_lhs >= compare_rhs is a pipeline invariant).
 
         m.submodules.pe = pe = PriorityEncoder(radix)
-        next_bits = Signal(log2_radix+1, reset_less=True)
+        next_bits = Signal(log2_radix, reset_less=True)
         m.d.comb += pe.i.eq(~pass_flags)
         with m.If(~pe.n):
             m.d.comb += next_bits.eq(pe.o-1)