more imports / syntax errors
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Jul 2019 08:11:42 +0000 (09:11 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Mon, 22 Jul 2019 08:11:42 +0000 (09:11 +0100)
src/ieee754/div_rem_sqrt_rsqrt/div_pipe.py
src/ieee754/fpdiv/divstages.py
src/ieee754/fpdiv/specialcases.py

index 2facb95aa9b8beb1fc3f80155abd465f590d6287..2c6ec33a3012874063bb6ccd36d84dd1f02f2d4a 100644 (file)
@@ -89,6 +89,7 @@ class DivPipeInterstageData(DivPipeCoreInterstageData, DivPipeBaseData):
 
     def eq(self, rhs):
         """ Assign member signals. """
+        print (self, rhs)
         return DivPipeCoreInterstageData.eq(self, rhs) + \
             DivPipeBaseData.eq(self, rhs)
 
@@ -131,8 +132,8 @@ class DivPipeBaseStage:
 class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
 
     def __init__(self, pspec):
-        DivPipeCoreSetupStage.__init__(self.get_core_config())
         self.pspec = pspec
+        DivPipeCoreSetupStage.__init__(self, pspec.core_config)
 
     def elaborate(self, platform):
         m = DivPipeCoreSetupStage(platform) # XXX TODO: out_do_z logic!
@@ -143,8 +144,8 @@ class DivPipeSetupStage(DivPipeBaseStage, DivPipeCoreSetupStage):
 class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
 
     def __init__(self, pspec, stage_index):
-        DivPipeCoreCalculateStage.__init__(self.get_core_config(), stage_index)
         self.pspec = pspec
+        DivPipeCoreCalculateStage.__init__(self, pspec.core_config, stage_index)
 
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
@@ -155,8 +156,8 @@ class DivPipeCalculateStage(DivPipeBaseStage, DivPipeCoreCalculateStage):
 class DivPipeFinalStage(DivPipeBaseStage, DivPipeCoreFinalStage):
 
     def __init__(self, pspec, stage_index):
-        DivPipeCoreFinalStage.__init__(self.get_core_config(), stage_index)
         self.pspec = pspec
+        DivPipeCoreFinalStage.__init__(self, pspec.core_config, stage_index)
 
     def elaborate(self, platform):
         m = DivPipeCoreCalculateStage(platform) # XXX TODO: out_do_z logic!
index 1b41b9e79dc0cdb84a61822acd3319e66705576e..914e77232a4d5dee11f62cec4530c867b96c95f1 100644 (file)
@@ -12,7 +12,11 @@ from nmutil.singlepipe import (StageChain, SimpleHandshake)
 from ieee754.fpcommon.fpbase import FPState
 from ieee754.fpcommon.denorm import FPSCData
 from ieee754.fpcommon.postcalc import FPAddStage1Data
-from ieee754.div_rem_sqrt_rsqrt.div_pipe import DivPipeInterstageData
+from ieee754.div_rem_sqrt_rsqrt.div_pipe import (DivPipeInterstageData,
+                                                 DivPipeSetupStage,
+                                                 DivPipeCalculateStage,
+                                                 DivPipeFinalStage,
+                                                )
 
 # TODO: write these
 from .div0 import FPDivStage0Mod
index d039eaaf303382134eed733cbab3632dcc8dd9c0..4a73e435c4704161aa3d7c39ba935a0de0ec8681 100644 (file)
@@ -101,7 +101,7 @@ class FPDIVSpecialCasesMod(Elaboratable):
             m.d.comb += self.o.out_do_z.eq(0)
 
         m.d.comb += self.o.oz.eq(self.o.z.v)
-        m.d.comb += self.o.mid.eq(self.i.mid)
+        m.d.comb += self.o.ctx.eq(self.i.ctx)
 
         return m