add progress counter

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 56f853c7f9a8f3a80c5e6800a9f77de7fc61d0ff..ee18ff2187ee504adfa161b7cc6d0cdccffb5e6b 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -44,7 +44,12 @@ class SinCosTestCase(FHDLTestCase):
             for i in range(40):
                 yield
         def reader_process():
+            counter = 200
             while True:
+                counter -= 1
+                if counter == 0: # some indication of progress
+                    print (".", sep="", end="", flush=True)
+                    counter = 200
                 yield
                 vld = yield dut.n.valid_o
                 if vld:
@@ -63,6 +68,8 @@ class SinCosTestCase(FHDLTestCase):
                     except StopIteration:
                         break
 
+            print() # newline after end of progress-indicator
+
         sim.add_sync_process(writer_process)
         sim.add_sync_process(reader_process)
         with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[