add LHS support into PartitionedCat. amazingly - stunningly - it works

https://bugs.libre-soc.org/show_bug.cgi?id=731

diff --git a/src/ieee754/part/test/minitest_partsig.py b/src/ieee754/part/test/minitest_partsig.py
index 830afa5ab5f1e304b95ff461a6eb51359ed0ea7e..611fd7ed899ee00a0e5684f154c579f45cf3fa55 100644 (file)
--- a/src/ieee754/part/test/minitest_partsig.py
+++ b/src/ieee754/part/test/minitest_partsig.py
@@ -44,19 +44,38 @@ if __name__ == "__main__":
         yield b.sig.eq(0x4567)
         yield Settle()
         out = yield o.sig
+        ao_1 = yield a1.sig
+        bo_1 = yield b1.sig
         print("out 000", bin(out&omask), hex(out&omask))
+        print("     a1 b1", hex(ao_1), hex(bo_1))
+        assert ao_1 == 0x123 and bo_1 == 0x4567
+
         yield mask.eq(0b010)
         yield Settle()
         out = yield o.sig
+        ao_1 = yield a1.sig
+        bo_1 = yield b1.sig
         print("out 010", bin(out&omask), hex(out&omask))
+        print("     a1 b1", hex(ao_1), hex(bo_1))
+        assert ao_1 == 0x123 and bo_1 == 0x4567
+
         yield mask.eq(0b110)
         yield Settle()
         out = yield o.sig
+        ao_1 = yield a1.sig
+        bo_1 = yield b1.sig
         print("out 110", bin(out&omask), hex(out&omask))
+        print("     a1 b1", hex(ao_1), hex(bo_1))
+        assert ao_1 == 0x123 and bo_1 == 0x4567
+
         yield mask.eq(0b111)
         yield Settle()
         out = yield o.sig
+        ao_1 = yield a1.sig
+        bo_1 = yield b1.sig
         print("out 111", bin(out&omask), hex(out&omask))
+        print("     a1 b1", hex(ao_1), hex(bo_1))
+        assert ao_1 == 0x123 and bo_1 == 0x4567
 
     sim.add_process(process)
     with sim.write_vcd("partition_minitest.vcd", "partition_partition_ass.gtkw",

diff --git a/src/ieee754/part_cat/cat.py b/src/ieee754/part_cat/cat.py
index 291575f4555d81563492ef59fc6e87e509104d12..1f42d3f034e191f77dc79988b2c0e4449cd90a42 100644 (file)
--- a/src/ieee754/part_cat/cat.py
+++ b/src/ieee754/part_cat/cat.py
@@ -71,6 +71,8 @@ class PartitionedCat(Elaboratable):
         self.width = width
         mask = ctx.get_mask()
         self.output = SimdSignal(mask, self.width, reset_less=True)
+        # XXX errr... this is a bit of a hack, but should work
+        # obtain the module for the output Signal
         self.output.set_module(ctx.psig.m)
         self.partition_points = self.output.partpoints
         self.mwidth = len(self.partition_points)+1
@@ -120,7 +122,10 @@ class PartitionedCat(Elaboratable):
                         output.append(thing)
                 with m.Case(pbit):
                     # direct access to the underlying Signal
-                    comb += self.output.sig.eq(Cat(*output))
+                    if self.is_lhs:
+                        comb += Cat(*output).eq(self.output.sig) # LHS mode
+                    else:
+                        comb += self.output.sig.eq(Cat(*output)) # RHS mode
 
         print ("PartitionedCat end")
         return m