Add asserts to fp pipe test

diff --git a/src/ieee754/cordic/pipe_data.py b/src/ieee754/cordic/pipe_data.py
index 83690e8d7656f480a36188211ca3cb40e6979078..c3f600ae1026aa982bdb04d5e9fe7462966f2a10 100644 (file)
--- a/src/ieee754/cordic/pipe_data.py
+++ b/src/ieee754/cordic/pipe_data.py
@@ -22,8 +22,8 @@ class CordicOutputData:
 
     def __init__(self, pspec, e_extra=False):
         width = pspec.width
-        self.x = FPNumBaseRecord(width, False, e_extra, name="x")
-        self.y = FPNumBaseRecord(width, False, e_extra, name="y")
+        self.x = Signal(width)
+        self.y = Signal(width)
         self.ctx = FPPipeContext(pspec)
         self.muxid = self.ctx.muxid
 

diff --git a/src/ieee754/cordic/test/test_fp_pipe.py b/src/ieee754/cordic/test/test_fp_pipe.py
index 9edfd58b348addd2f67255802b4766c0291f582b..698efc95a65ca0fba7895f772b0bcf4bd2df3d1a 100644 (file)
--- a/src/ieee754/cordic/test/test_fp_pipe.py
+++ b/src/ieee754/cordic/test/test_fp_pipe.py
@@ -12,13 +12,11 @@ import random
 
 
 class SinCosTestCase(FHDLTestCase):
-    def run_test(self, inputs):
+    def run_test(self, inputs, outputs=iter([])):
         m = Module()
         pspec = FPCordicPipeSpec(width=32, rounds_per_stage=4, num_rows=1)
         m.submodules.dut = dut = FPCordicBasePipe(pspec)
 
-        for port in dut.ports():
-            print ("port", port)
 
         # vl = rtlil.convert(dut, ports=dut.ports())
         # with open("test_cordic_pipe_sin_cos.il", "w") as f:
@@ -39,35 +37,55 @@ class SinCosTestCase(FHDLTestCase):
 
         def writer_process():
             for val in inputs:
-                print(val)
                 yield z.eq(val.bits)
                 yield z_valid.eq(1)
                 yield ready.eq(1)
                 yield
             for i in range(40):
                 yield
+        def reader_process():
+            while True:
+                yield
+                vld = yield dut.n.valid_o
+                if vld:
+                    try:
+                        sin, cos = outputs.__next__()
+                        result = yield dut.n.data_o.x
+                        result = Float32(result)
+                        msg = f"cos: expected {cos} got {result}"
+                        self.assertLess(abs(result - Float32(cos)),
+                                        Float32(2e-7), msg=msg)
+                        result = yield dut.n.data_o.y
+                        result = Float32(result)
+                        msg = f"sin: expected {sin} got {result}"
+                        self.assertLess(abs(result - Float32(sin)),
+                                        Float32(2e-7), msg=msg)
+                    except StopIteration:
+                        break
 
         sim.add_sync_process(writer_process)
+        sim.add_sync_process(reader_process)
         with sim.write_vcd("fp_pipeline.vcd", "fp_pipeline.gtkw", traces=[
                 z]):
             sim.run()
 
     def test_rand(self):
-        fracbits = 16
-        M = (1 << fracbits)
-        ZMAX = int(round(M * math.pi/2))
         inputs = []
-        for i in range(-5, 10, 1):
-            if i < 0:
-                inputs.append(Float32(-2.0**(-abs(i))))
-            else:
-                inputs.append(Float32(2.0**(-abs(i))))
-        self.run_test(iter(inputs))
+        for i in range(20000):
+            x = random.uniform(-1, 1)
+            inputs.append(Float32(x))
+        sines = [math.sin(x * Float32(math.pi/2)) for x in inputs]
+        cosines = [math.cos(x * Float32(math.pi/2)) for x in inputs]
+        outputs = zip(sines, cosines)
+        self.run_test(iter(inputs), outputs=iter(outputs))
 
     def test_pi_2(self):
         inputs = [Float32(0.5), Float32(1/3), Float32(2/3),
                   Float32(-.5), Float32(0.001)]
-        self.run_test(iter(inputs))
+        sines = [math.sin(x * Float32(math.pi/2)) for x in inputs]
+        cosines = [math.cos(x * Float32(math.pi/2)) for x in inputs]
+        outputs = zip(sines, cosines)
+        self.run_test(iter(inputs), outputs=iter(outputs))
 
 
 if __name__ == "__main__":