set reset_less=True - the data is protected by muxid. if muxid not set,

data is invalid.  therefore reset is pointless (and wastes gates)

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 3d58d0debdb493be0c88c93fb3b80ddca0afbf82..0ee393510bbb92746f71e721030c5e9ab8f2b142 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -144,10 +144,10 @@ class DivPipeCoreTestPipeline(Elaboratable):
             for stage_index in range(core_config.num_calculate_stages)]
         self.final_stage = DivPipeCoreFinalStage(core_config)
         self.interstage_signals = [
-            DivPipeCoreInterstageData(core_config, reset_less=False)
+            DivPipeCoreInterstageData(core_config, reset_less=True)
             for i in range(core_config.num_calculate_stages + 1)]
-        self.i = DivPipeCoreInputData(core_config, reset_less=False)
-        self.o = DivPipeCoreOutputData(core_config, reset_less=False)
+        self.i = DivPipeCoreInputData(core_config, reset_less=True)
+        self.o = DivPipeCoreOutputData(core_config, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()