whoops missed set up of temp variable bw

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index a6a65cc8a35703cc1761172e6150fb5350eea88a..c407626603de89602a84ebed4016d3fc16f3f00f 100644 (file)
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -224,6 +224,7 @@ class DivPipeCoreSetupStage(Elaboratable):
         self.core_config = core_config
         self.i = self.ispec()
         self.o = self.ospec()
+        bw = core_config.bit_width
         if core_config.supported == [DP.UDivRem]:
             self.compare_len = bw * 2
         else: