From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 22 Jul 2019 10:19:13 +0000 (+0100)
Subject: remove stage-work-reduction for now
X-Git-Tag: ls180-24jan2020~776
X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=commitdiff_plain;h=838418d03759a8a457e1f15c819b95ddea8aac1d

remove stage-work-reduction for now
---

diff --git a/src/ieee754/fpdiv/pipeline.py b/src/ieee754/fpdiv/pipeline.py
index 416bcd99..40bdedf6 100644
--- a/src/ieee754/fpdiv/pipeline.py
+++ b/src/ieee754/fpdiv/pipeline.py
@@ -98,12 +98,12 @@ class FPDIVBasePipe(ControlBase):
             # needs to convert input from pipestart ospec
             if i == 0:
                 kls = FPDivStagesSetup
-                n_comb_stages -= 1  # reduce due to work done at start
+                #n_comb_stages -= 1  # reduce due to work done at start?
 
             # needs to convert output to pipeend ispec
             elif i == n_stages - 1:
                 kls = FPDivStagesFinal
-                n_comb_stages -= 1  # FIXME - reduce due to work done at end?
+                #n_comb_stages -= 1  # FIXME - reduce due to work done at end?
 
             # intermediary stage
             else: