From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 19 Jul 2019 11:45:56 +0000 (+0100)
Subject: weirdness on INT32->FP32 detected.  ui32/i32->f32 test added
X-Git-Tag: ls180-24jan2020~808
X-Git-Url: https://git.libre-soc.org/?p=ieee754fpu.git;a=commitdiff_plain;h=d93975e80a3ae0f2b38d307ae91336095303cc4b

weirdness on INT32->FP32 detected.  ui32/i32->f32 test added
---

diff --git a/src/ieee754/fcvt/pipeline.py b/src/ieee754/fcvt/pipeline.py
index c22f9fbf..85432ca7 100644
--- a/src/ieee754/fcvt/pipeline.py
+++ b/src/ieee754/fcvt/pipeline.py
@@ -107,10 +107,16 @@ class FPCVTIntToFloatMod(Elaboratable):
         m.d.comb += msb.m_in.eq(Cat(0, 0, 0, mantissa)) # g/r/s + input
         m.d.comb += msb.e_in.eq(me)                     # exp = int width
 
-        if ms < 0:
-            # larger int to smaller FP (uint32/64 -> fp16 most likely)
+        # to do with FP16... not yet resolved why
+        alternative = ms < 0
+
+        if alternative:
             m.d.comb += z1.e.eq(msb.e_out-1)
-            m.d.comb += z1.m[ms-1:].eq(msb.m_out[-mz-1:])
+            if mz == 16:
+                # larger int to smaller FP (uint32/64 -> fp16 most likely)
+                m.d.comb += z1.m[ms-1:].eq(msb.m_out[-mz-1:])
+            else: # 32? XXX weirdness...
+                m.d.comb += z1.m.eq(msb.m_out[-mz-1:])
         else:
             # smaller int to larger FP
             m.d.comb += z1.e.eq(msb.e_out)
@@ -128,7 +134,7 @@ class FPCVTIntToFloatMod(Elaboratable):
         # is even necessary.  it probably isn't
 
         # initialise rounding (but only activate if needed)
-        if ms < 0:
+        if alternative:
             # larger int to smaller FP (uint32/64 -> fp16 most likely)
             m.d.comb += self.o.of.guard.eq(msb.m_out[-mz-2])
             m.d.comb += self.o.of.round_bit.eq(msb.m_out[-mz-3])
diff --git a/src/ieee754/fcvt/test/test_fcvt_int_pipe.py b/src/ieee754/fcvt/test/test_fcvt_int_pipe.py
index 4f72f83a..857432b0 100644
--- a/src/ieee754/fcvt/test/test_fcvt_int_pipe.py
+++ b/src/ieee754/fcvt/test/test_fcvt_int_pipe.py
@@ -39,6 +39,10 @@ def fcvt_i16_f32(x):
     print ("fcvt i16_f32", hex(x))
     return sfpy.float.i32_to_f32(x) # XXX no i16_to_f32, it's ok though
 
+def fcvt_i32_f32(x):
+    print ("fcvt i32_f32", hex(x))
+    return sfpy.float.i32_to_f32(x)
+
 def fcvt_i32_f64(x):
     print ("fcvt i32_f64", hex(x))
     return sfpy.float.i32_to_f64(x)
@@ -68,6 +72,11 @@ def test_int_pipe_i32_f64():
     runfp(dut, 32, "test_fcvt_int_pipe_i32_f64", to_int32, fcvt_i32_f64, True,
           n_vals=100, opcode=0x1)
 
+def test_int_pipe_i32_f32():
+    dut = FPCVTIntMuxInOut(32, 32, 4, op_wid=1)
+    runfp(dut, 32, "test_fcvt_int_pipe_i32_f32", to_int32, fcvt_i32_f32, True,
+          n_vals=100, opcode=0x1)
+
 ######################
 # unsigned int to fp
 ######################
@@ -84,6 +93,11 @@ def test_int_pipe_ui16_f64():
     runfp(dut, 16, "test_fcvt_int_pipe_ui16_f64", to_uint16, fcvt_64, True,
           n_vals=100)
 
+def test_int_pipe_ui32_f32():
+    dut = FPCVTIntMuxInOut(32, 32, 4, op_wid=1)
+    runfp(dut, 32, "test_fcvt_int_pipe_ui32_32", to_uint32, fcvt_32, True,
+          n_vals=100)
+
 def test_int_pipe_ui32_f64():
     dut = FPCVTIntMuxInOut(32, 64, 4, op_wid=1)
     runfp(dut, 32, "test_fcvt_int_pipe_ui32_64", to_uint32, fcvt_64, True,
@@ -115,9 +129,12 @@ def test_int_pipe_ui32_f16():
 
 if __name__ == '__main__':
     for i in range(200):
-        test_int_pipe_i32_f64()
+        test_int_pipe_ui32_f32()
+        test_int_pipe_i32_f32()
         continue
         test_int_pipe_i16_f32()
+        test_int_pipe_i32_f64()
+        continue
         test_int_pipe_ui16_f32()
         test_int_pipe_ui64_f32()
         test_int_pipe_ui32_f16()
diff --git a/src/ieee754/fpcommon/test/fpmux.py b/src/ieee754/fpcommon/test/fpmux.py
index c294f159..181e57a2 100644
--- a/src/ieee754/fpcommon/test/fpmux.py
+++ b/src/ieee754/fpcommon/test/fpmux.py
@@ -161,6 +161,8 @@ def create_random(num_rows, width, single_op=False, n_vals=10):
 
                 #op1 = 0x1841
 
+                #op1 = 0x3449f9a9
+
                 vals.append((op1,))
             else:
                 op1 = randint(0, (1<<width)-1)