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[ieee754fpu.git] / src / ieee754 / div_rem_sqrt_rsqrt / core.py
2020-07-20 Jacob Lifshaydisable faulty bit_width reduction logic in DivPipeCore
2020-07-13 Jacob Lifshayclean up DivPipeCoreConfig API
2020-07-10 Luke Kenneth Casso... whoops missed set up of temp variable bw
2020-07-10 Luke Kenneth Casso... only pass in lhs bit_width * 2 for UDivRem
2020-07-04 Luke Kenneth Casso... continue reducing length of signals in div core
2020-07-04 Luke Kenneth Casso... reduce compare lengths to *2 rather than *3
2020-07-04 Luke Kenneth Casso... whoops set pass_flag[0] always true
2020-07-03 Luke Kenneth Casso... cut top trial comparison
2020-07-03 Luke Kenneth Casso... remove use of Array, replace with treereduce
2020-07-03 Luke Kenneth Casso... cut root_times_radicand if not doing Sqrt
2020-07-03 Luke Kenneth Casso... add "supported" option to div core
2020-01-17 Luke Kenneth Casso... min/max in Signal deprecated in nmigen
2019-07-30 Luke Kenneth Casso... remove default and swap over DIV/SQRT operations, to...
2019-07-30 Luke Kenneth Casso... use switch/case rather than if/elif/elif
2019-07-29 Luke Kenneth Casso... minor tidyup
2019-07-29 Luke Kenneth Casso... add explicit operator comparison (in case operation...
2019-07-29 Luke Kenneth Casso... clarify / get indentation down
2019-07-29 Luke Kenneth Casso... replace m.d.comb with comb (reduce indentation)
2019-07-28 Luke Kenneth Casso... add debug prints
2019-07-25 Jacob LifshayRevert "reduce LHS for RSQRT by a factor of fract_width...
2019-07-24 Luke Kenneth Casso... fix shifting of rsqrt mantissa input
2019-07-24 Luke Kenneth Casso... reduce LHS for RSQRT by a factor of fract_width and
2019-07-23 Luke Kenneth Casso... more comments
2019-07-23 Luke Kenneth Casso... reduce next_bits by 1
2019-07-23 Luke Kenneth Casso... clean up comments
2019-07-23 Luke Kenneth Casso... use PriorityEncoder and Array selection
2019-07-23 Luke Kenneth Casso... store bits in signals, cleans up graphviz
2019-07-23 Luke Kenneth Casso... split out div/sqrt/rsqrt trials to separate module
2019-07-23 Luke Kenneth Casso... tidyup a bit
2019-07-22 Luke Kenneth Casso... remove FIXMEs
2019-07-22 Luke Kenneth Casso... rename long parameter name to shorter n_stages
2019-07-22 Luke Kenneth Casso... compare_rhs is a multi-bit value (cant use bool())
2019-07-21 Luke Kenneth Casso... restore important modifications that seemed to be lost
2019-07-10 Jacob LifshayDivPipeCore tests pass; still need to add more tests
2019-07-10 Jacob Lifshaytest_core.py doesn't crash anymore
2019-07-09 Jacob Lifshayrename log2_tb -> tb_width
2019-07-07 Luke Kenneth Casso... add missing reset_lesss
2019-07-07 Luke Kenneth Casso... exclude stuff that is just multiplying by zero
2019-07-07 Luke Kenneth Casso... clarify if else
2019-07-07 Luke Kenneth Casso... add names to flags
2019-07-07 Luke Kenneth Casso... whitespace
2019-07-07 Luke Kenneth Casso... add comment
2019-07-07 Luke Kenneth Casso... sort out some magic constants
2019-07-07 Luke Kenneth Casso... workaround issue with nmigen/yosys
2019-07-07 Jacob Lifshaywork on adding tests; test_core.py currently fails
2019-07-07 Jacob Lifshaymisc code cleanups
2019-07-07 Jacob Lifshaymove DivPipe(?!Core).* classes to div_pipe.py
2019-07-05 Luke Kenneth Casso... big (single-purpose) update: move width arg into pspec
2019-07-05 Luke Kenneth Casso... move Base eqs to separate mixin class
2019-07-05 Luke Kenneth Casso... add inheritor classes to create DivPipe*Data
2019-07-05 Jacob Lifshayadd rest of DivPipeCore
2019-07-05 Luke Kenneth Casso... add in more comments
2019-07-05 Luke Kenneth Casso... add FPPipeContext/FPNumBaseRecord import
2019-07-05 Luke Kenneth Casso... all modules need to carry an output bypass plus a conte...
2019-07-05 Jacob Lifshayfix up setup and process functions
2019-07-05 Luke Kenneth Casso... link in to setup/process
2019-07-05 Jacob Lifshayadd DivPipeCoreSetupStage