180nm_Oct2020.mdwn

   1 # 180 nm ASIC plan for Oct 2020
   2
   3 This page is for discussion of what we can aim for and reasonably achieve.
   4 To be expanded with links to bugreports
   5
   6 Links:
   7
   8 * <https://gitlab.com/Chips4Makers>
   9 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html>
  10
  11 ## Minimum viability
  12
  13 * a Wishbone interface.  this allows us to drop *directly* into
  14   already-written Litex "SOC" infrastructure (leaving all of us free to
  15   focus on the essentials)
  16 * the dependency matrices are essential.
  17 * a Branch Function Unit is essential (minimum of 1)
  18 * Load/Store Function Units are essential
  19 * so are multiple register file files (SPRs, Condition Regs, 32x INT Regs)
  20 * the integer pipelines (integer and logic instructions) are essential
  21   (the FP ones not so much)
  22   <https://bugs.libre-soc.org/show_bug.cgi?id=305>
  23 * a very very basic Branch Prediction system (fixed, but observing POWER
  24   branch "hints")
  25 * a very very basic Common Data Bus infrastructure.
  26 * a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
  27 * neither in some ways is a L1 cache
  28 * [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
  29   GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
  30   and that actually might even be it.
  31 * [[180nm_Oct2020/ls180]] actual auto-generated pinouts by pinmux program
  32
  33 ## Secondary priorities
  34
  35 * a PLL (this is quite a lot however it turns the ASIC from a 24mhz
  36   design into a 300mhz design)
  37 * a TLB and MMU (in combination with a PLL if it is GNU/Linux OS capable
  38   we have an actual viable *saleable product*, immediately)
  39 * dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
  40 * multiple Common Data Buses to / from the RegFile along with a 4x
  41   "Striped" HI/LO-32-ODD/EVEN access pattern.
  42 * multi-issue
  43 * PartitionedSignal-based integer pipelines
  44 * an FP regfile and associated FP pipelines
  45 * SV compliance
  46 * 128x INT/FP registers
  47 * GPU-style opcodes - Jacob mentioned Texturisation opcodes as being
  48   more important than e.g. SIN/COS.
  49 * additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
  50   USB-ULPI
  51 * a pinmux
  52 * [FSI instead of JTAG](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/blob/master/fsi_master.v)
  53
  54 # Available people
  55
  56 * Rudi from <http://asics.ws> to cover the interface set
  57 * [[lkcl]] for the scoreboard systems
  58 * [[programmerjake]] TODO
  59 * [[Yehowshua_Immanuel]] - Delegate interfaces and do timeline/cost projections
  60 * [[mnolan]] pipelines
  61 * [[tplaten]] memory and cache
  62 * [[jock_tanner]] TODO
  63 * MarketNext TODO
  64
  65 # Preliminary coriolis2 ASIC layout
  66
  67 ## 02jul2020 - first version
  68
  69 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008438.html>
  70
  71 [[!img 180nm_Oct2020/2020-07-02_19-01.png size="900x" ]]
  72
  73 ## 03jul2020 - DIV unit added
  74
  75 [[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]
  76
  77 ## 28dec2020 - End of year progress update
  78
  79 ### With blockage layers
  80
  81 [[!img 180nm_Oct2020/2020-12-28.png size="900x" ]]
  82
  83 ### Without blockage layers so wires can be seen more clearly
  84
  85 [[!img 180nm_Oct2020/2020-12-28_without_blockages.png size="900x" ]]