interrupts.mdwn

   1 # Interrupt Handling for RISC-V
   2
   3 This page is a non-authoritative resource for information and documentation
   4 about interrupt handling on RISC-V.  An interim page for the discussion
   5 of interrupt handling is here: [[interrupt_handling]].
   6
   7 # Open PLIC Implementations
   8
   9 * <https://github.com/RoaLogic/plic> - written in verilog, has an
  10     AHB3-Lite / AMBA interface.  Documentation is here:
  11     <https://github.com/RoaLogic/plic/blob/master/DATASHEET.md>
  12     It has been taped out, it supports virtually unlimited (limited by
  13     timing only) IRQ lines.  All registers are dynamically generated.
  14     Currently it only features an AHB3 slave interface, but the BIU is
  15     separate. So other interfaces can be easily added.
  16 * Shakti Peripherals, there is a tested (taped-out) version here
  17   in src/peripherals/plic <https://bitbucket.org/casl/c-class/src/>
  18   and another version with up to 1024 IRQ lines and a 2-cycle
  19   response time here <http://git.libre-riscv.org/?p=shakti-peripherals.git;a=tree;f=src/peripherals/plic>