openpower.mdwn

   1 # OpenPOWER
   2
   3 In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
   4 This evolved to a specification known as the Power ISA. In 2019 IBM made the Power ISA [[!wikipedia Open_source]] to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]].
   5
   6 Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on OpenPOWER because it wants to be able to specify a machine that can be completely trusted, and because OpenPOWER is designed for high performance.
   7
   8 # Evaluation
   9
  10 EULA released! looks good.
  11
  12 Links
  13
  14 * OpenPOWER Membership
  15   <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
  16 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
  17 * [[openpower/isatables]]
  18 * [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
  19 * [[openpower/gem5]]
  20 * [[openpower/sv]]
  21 * [[openpower/simd_vsx]]
  22 * [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
  23 * [[openpower/pearpc]]
  24 * [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
  25 * [[3d_gpu/architecture/decoder]]
  26 * <https://forums.raptorcs.com/>
  27 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  28 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  29 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  30 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  31 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  32
  33 PowerPC Unit Tests
  34
  35 * <https://github.com/lioncash/DolphinPPCTests>
  36 * <https://github.com/JustinCB/macemu/blob/master/SheepShaver/src/kpx_cpu/src/test/test-powerpc.cpp>
  37
  38 Summary
  39
  40 * FP32 is converted to FP64. Requires SimpleV to be active.
  41 * FP16 needed
  42 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  43 * FCVT between 16/32/64 needed
  44 * c++11 atomics not very efficient
  45 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  46 * needs escape sequencing (ISAMUX/NS) - see [[openpower/isans_letter]]
  47
  48 # What we are *NOT* doing:
  49
  50 * A processor that is fundamentally incompatible (noncompliant) with Power.
  51  (**escape-sequencing requires and guarantees compatibility**).
  52 * Opcode 4 Signal Processing (SPE)
  53 * Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
  54 * Avoidable legacy opcodes
  55
  56 # SimpleV
  57
  58 see [[openpower/sv]].
  59 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  60 register files to "a sequence of elements".  The **one** instruction
  61 (an unmodified **scalar** instruction) is interpreted as a *hardware
  62 for-loop* that issues **multiple** internal instructions with
  63 sequentially-incrementing register numbers.
  64
  65 Thus it is completely unnecessary to add any vector opcodes - at all -
  66 saving hugely on both hardware and compiler development time when
  67 the concept is dropped on top of a pre-existing ISA.
  68
  69 ## Condition Registers
  70
  71 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  72
  73 ## Carry
  74
  75 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Most sensible location to use is the CRs
  76
  77 # Integer Overflow / Saturate
  78
  79 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  80
  81 # atomics
  82
  83 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  84
  85 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  86
  87 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  88
  89 # FP16
  90
  91 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  92
  93 Usually done with a fmt field, 2 bit, last one is FP128
  94
  95 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  96
  97 # Escape Sequencing
  98
  99 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
 100 from OpenPower Foundation.
 101
 102 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
 103 (including for and by OpenPower Foundation)
 104
 105 ## Branches in namespaces
 106
 107 Branches are fine as it is up to the compiler to decide whether to let the
 108 ISAMUX/NS/escape-sequence countdown run out.
 109
 110 This is all a software / compiler / ABI issue.
 111
 112 ## Function calls in namespaces
 113
 114 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
 115
 116 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
 117
 118 All of this is a software issue (compiler / ABI).
 119
 120 # Compressed, 48, 64, VBLOCK
 121
 122 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 123
 124 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 125 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 126
 127 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 128 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 129 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 130 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 131
 132 Note that this requires BE instruction encoding (separate from
 133 data BE/LE encoding).  BE encoding always places the major opcode in
 134 the first 2 bytes of the raw (uninterpreted) sequential instruction
 135 byte stream.
 136
 137 Thus in BE-instruction-mode, the first 2 bytes may be analysed to
 138 detect whether the instruction is 16-bit Compressed, 48-bit SVP-P48,
 139 64-bit SVP-64, variable-length VBLOCK, or plain 32-bit.
 140
 141 It is not possible to distinguish LE-encoded 32-bit instructions
 142 from LE-encoded 16-bit instructions because in LE-encoded 32-bit
 143 instructions, the opcode falls into:
 144
 145 * bytes 2 and 3 of any given raw (uninterpreted) sequential instruction
 146   byte stream for a 32-bit instruction
 147 * bytes 0 and 1 for a 16-bit Compressed instruction
 148 * bytes 4 and 5 for a 48-bit SVP P48
 149 * bytes 6 and 7 for a 64-bit SVP P64
 150
 151 Clearly this is an impossible situation, therefore BE is the only
 152 option.  Note: *this is completely separate from BE/LE for data*
 153
 154 # Compressed 16
 155
 156 Further "escape-sequencing".
 157
 158 Only 11 bits available. Idea: have "pages" where one instruction selects
 159 the page number. It also specifies for how long that page is activated
 160 (terminated on a branch)
 161
 162 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 163
 164 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 165
 166 Store activation length in a CSR.
 167
 168 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 169
 170 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 171
 172 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 173
 174 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 175