openpower/isans_letter.mdwn

   1
   2 # Letter regarding ISAMUX / NS
   3
   4 * Revision 0.0 draft: 03 Mar 2020
   5 * Revision 0.9 pre-final: 18 Apr 2020
   6
   7 ## Why has Libre-SOC chosen PowerPC ?
   8
   9 For a hybrid CPU-VPU-GPU, intended for mass-volume adoption in tablets,
  10 netbooks, chromebooks and industrial embedded (SBC) systems, our choice
  11 was between Nyuzi, MIAOW, RISC-V, PowerPC, MIPS and OpenRISC.
  12
  13 Of all the options, the PowerPC architecture is more complete and far more
  14 mature.  It also has a deeper adoption by Linux distributions.
  15
  16 Following IBM's release of the Power Architecture instruction set to the
  17 Linux Foundation in August 2019 the barrier to using it is no more than
  18 that of using RISC-V.  We are encouraged that the OpenPOWER Foundation is
  19 supportive of what we are doing and helping, e.g by putting us in touch
  20 with people who can help us.
  21
  22 ## Summary
  23
  24 * We propose the standardisation of the way that the PowerPC Instruction
  25   Set Architecture (PPC ISA) is extended, enabling many different flavours
  26   within a well supported family to co-exist, long-term, without conflict,
  27   right across the board.
  28 * This is about more than just our project. Our proposals will facilitate
  29   the use of PPC in novel or niche applications without breaking the PPC
  30   ISA into incompatible islands.
  31 * PPC will gain a competitive market advantage by removing the need
  32   for separate VPU or GPU functions in RTL or ASICs thus enabling lower
  33   cost systems.  Libre-SOC's project is to extend the PPC to integrate
  34   the GPU and VPU functionality directly as part of the PPC ISA (example:
  35   Broadcom VideoCore IV being based around extensions to an ARC core).
  36 * Libre-SOC's extensions will be easily adopted, as the standard GNU/Linux
  37   distributions will very deliberately run unmodified on our ISA,
  38   including full compatibility with illegal instruction trap requirements.
  39
  40 ## One CPU multiple ISAs
  41
  42 This is a quick overview of the way that we would like to add changes
  43 that we are proposing to the PowerPC instruction set (ISA).  It is based on
  44 a Open Standardisation of the way that existing "mode switches",
  45 already found in the POWER instruction set, are added:
  46
  47 * FPSCR's "NI" bit, setting non-IEEE754 FP mode
  48 * MSR's "LE" bit (and associated HILE bit), setting little-endian mode
  49 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
  50 * PCR's "compatibility" bits 60-62, V2.05 V2.06 V2.07 mode
  51
  52 [It is well-noted that unless each "mode switch" bit is set, any
  53 alternative (additional) instructions (and functionality) are completely
  54 inaccessible, and will result in "illegal instruction" traps being thrown.
  55 This is recognised as being critically important.]
  56
  57 These bits effectively create multiple, incompatible run-time switchable ISAs
  58 within one CPU.  They are selectable for the needs of the individual
  59 program (or OS) being run.
  60
  61 All of these bits are set by an instruction, that, once set, radically
  62 changes the entire behaviour and characteristics of subsequent instructions.
  63
  64 With these (and other) long-established precedents already in POWER,
  65 there is therefore essentially conceptually nothing new about what we
  66 propose: we simply seek that the process by which such "switching" is
  67 added is formalised and standardised, such that we (and others, including
  68 IBM itself) have a clear, well-defined standards-non-disruptive, atomic
  69 and non-intrusive path to extend the POWER ISA for use in markets that
  70 it presently cannot enter.
  71
  72 We advocate that some of "mode-setting" (escape-sequencing) bits be
  73 binary encoded, some unary encoded, and that some space marked for
  74 "offical" use, some "experimental", some "custom" and some "reserved".
  75 The available space in a suitably-chosen SPR to be formalised, and
  76 recommend the OpenPOWER Foundation be given the IANA-like role in
  77 atomically allocating mode bits.
  78
  79 Instructions that we need to add, which are a normal part of GPUs,
  80 include ATAN2, LOG, NORMALISE, YUV2RGB, Khronos Compliance FP mode
  81 (different from both IEEE754 and "NI" mode), and many more.  Many of
  82 these may turn out to be useful in a wider context: they however need
  83 to be fully isolated behind "mode-setting".
  84
  85 Some mode-setting instructions are privileged, ie can only be set by
  86 the kernel (eg 32 or 64 bit mode). Most of the escape sequences that we
  87 propose will be (have to be) usable without the need for an expensive
  88 system call overhead (because some of the instructions needed will be
  89 in extremely tight inner loops).
  90
  91 # About Libre-SOC Commercial Project
  92
  93 The Libre-SOC Commercial Product is a hybrid GPU-GPU-VPU intended for
  94 mass-volume production.  There is no separate GPU, because the CPU
  95 *is* the GPU.  There is no separate VPU, because the CPU *is* the GPU.
  96 There is not even a separate pipeline: the CPU pipelines *are* the
  97 GPU and VPU pipelines.
  98
  99 Closest equivalents include the ARC core (which has VPU extensions and
 100 3D extensions in the form of Broadcom's VideoCore IV) and the ICubeCorp
 101 IC3128.  Both are considered "hybrid" CPU-GPU-VPU processors.
 102
 103 "Normal" Commercial GPUs are entirely separate processors.  The development
 104 cost and complexity purely in terms of Software Drivers alone is immense.
 105 We reject that approach (and as a small team we do not have the resources
 106 anyway).
 107
 108 With the project being Libre - not proprietary and secretive and never
 109 to be published, ever - it is no good having the extensions as "custom"
 110 because "custom" is specifically for the cases where the augmented
 111 toolchain is never, under any circumstances, published and made public by
 112 the proprietary company (and would never be accepted upstream anyway).
 113 For business commercial reasons, Libre-SOC is the total opposite of this
 114 proprietary, secretive approach.
 115
 116 Therefore, to meet our business objectives:
 117
 118 * As shown from Nyuzi and Larrabee, although ideally suited to high
 119   performance compute tasks, a "traditional" general-purpose full
 120   IEEE754-compliant Vector ISA (such as that in POWER9) is not an adequate
 121   basis for a commercially competitive GPU.  Nyuzi's conclusion is that
 122   using such general-purpose Vector ISAs results in reaching only 25%
 123   performance (or requiring 4-fold increase in power consumption) to
 124   achieve par with current commercial-grade GPUs.
 125 * We are not going the "traditional" (separate custom GPU) route because
 126   it is not practical for a new team to design hardware and spend 8+
 127   man-years on massively complex inter-processor driver development as well
 128 * We cannot meet our objectives with a "custom extension" because the
 129   financial burden on our team to maintain a total hard fork of not just
 130   toolchains, but also entire GNU/Linux Distros, is highly undesirable,
 131   and completely impractical (we know for certain that Redhat would
 132   strongly object to any efforts to hard-fork Fedora)
 133 * We cannot "go ahead anyway" because to do so would be highly irresponsible
 134   and cause massive disruption to the POWER community.
 135
 136 With all impractical options eliminated the only remaining responsible
 137 option is to extend the POWER ISA in an atomically-managed (IANA-style)
 138 formal fashion, whilst (critically and absolutely essentially) always
 139 providing a PCR compatibility mode that is fully POWER compliant, including
 140 all illegal instruction traps.
 141