openpower/isans_letter.mdwn

   1 # Letter regarding ISAMUX / NS
   2
   3 This is a quick overview of the changes that we are proposing to the PowerPC
   4 instruction set.
   5
   6 ## Overview
   7
   8 The PowerPC Instruction Set Architecture (ISA) is an abstract model of a
   9 computer. This is what programmers use when they write programs for the machine,
  10 even if indirectly via a compiler for a high level language. We must be
  11 conservative in how we add to the ISA to:
  12
  13 * not break existing programs
  14
  15 * be mindful as to how others may wish to add to the ISA in the future
  16
  17 This document describes our strategy.
  18
  19
  20 ## ISA modes and escape sequences
  21
  22 New chips usually need to be able to run older (legacy) software that is
  23 incompatible with the latest and greatest ISA. Eg: 64 bit chip must be able to
  24 run older 16 bit and 32 bit software.
  25
  26 To enable backwards compatability the CPU will be set into 'legacy' mode. This
  27 is done with an ISA Mode switch, also known as ISA Muxing or ISA Namespaces.
  28
  29 The operating system is able to quickly change between 'modern' ISA mode and
  30 various legacy modes.
  31
  32 Another technique is an ISA escape-sequence. This is a type of mode that is
  33 only operational for a short time, unlike 32 or 64 bit which would be for the
  34 entire run of a program.
  35
  36
  37 ## What are we adding to the ISA
  38
  39 When high quality graphical display were developed the CPUs at the time were
  40 shown to not be able to run the display fast enough. The solution was the use of
  41 Graphics cards, these are specialised computers that are good at rendering
  42 pixels; often by doing the same thing in different parts of the screen at the
  43 same time (in parallel). These specialised computers are called Graphical
  44 Processing Units (GPUs).
  45
  46 The parallelism of some GPUs is thousands. This has led to GPUs being used to
  47 solve non graphical problems where high parallelism is useful.
  48
  49 **break**
  50
  51 # Letter regarding ISAMUX / NS
  52
  53 Hardware-level dynamic ISA Muxing (also known as ISA Namespaces and ISA
  54 escape-sequencing) is commonly used in instruction sets, in an arbitrary
  55 and ad-hoc fashion, added often on an on-demand basis.  Examples include:
  56
  57 * Setting a SPR to switch the meaning of certain opcodes for Little-Endian /
  58   Big-Endian behaviour (present in POWER and SPARC)
  59 * Setting a SPR to provide "backwards-compatibility" for features from
  60   older versions of an ISA (such as changing to new ratified versions of
  61   the IEEE754 standard)
  62
  63 (These we term "ISA Muxing" because, ultimately, they are extra bits
  64 (or change existing bits) in the actual instruction decoder phase,
  65 which involves "MUXes" to switch them on and off).
  66
  67 The Libre-SOC team, developing a hybrid CPU-VPU-GPU, needs to add
  68 significantly and strategically to the POWER ISA to support, for example,
  69 Khronos Vulkan IEEE754 Conformance, whilst *at the same time being able
  70 to run full POWER9 compliant instructions*.
  71
  72 There is absolutely no way that we are going to duplicate the
  73 entire FP opcode set as a custom extension to POWER, just to add a
  74 literally-identical suite of FP opcodes that are compliant with the
  75 Khronos Conformance Suites: this would be a significant and irresponsible
  76 use of opcode space.
  77
  78 In addition, as this processor is likely to be used for parallel
  79 compute purposes in high-efficiency environments, we also need to add
  80 FP16 support.  Again: there is no way that we are going to add *triple*
  81 duplicated opcodes to POWER, given that the opcodes needed are absolutely
  82 identical to those that already exist, apart from the FP bitwidth (32
  83 / 64).
  84
  85 There are several other strategically critical uses to which we would
  86 like to put such a scheme (related to power consumption and reducing
  87 throughput bottlenecks needed for heavy-computation workloads in GPU
  88 and VPU scenarios).
  89
  90 In addition, the scheme has several other key advantages over other ISA
  91 "extending" ideas (such as extending the general ISA POWER space to
  92 64 bit) in that, unlike 64 bit opcodes, its judicious and careful use
  93 does not require large increases in I-Cache size because all opcodes,
  94 ultimately, remain 32-bit.  The scheme also allows future *official*
  95 POWER extensions to the ISA - managed by the OpenPOWER Foundation -
  96 to be strategically managed in a controlled, long-term, non-damaging
  97 way to the reputation and stability of OpenPOWER.
  98
  99 Therefore we advocate being able to set "ISAMUX/NS" mode-switching bits
 100 that, like the *existing* LE/BE mode-switching bits, change the behaviour
 101 of *existing* opcodes to an alternative "meaning" (followed by another
 102 mode-switch that returns them to their original meaning. Note: to reduce
 103 binary code-size, alternative schemes include setting a countdown which,
 104 when it expires, automatically disables the requested mode-switch)
 105
 106 Note also that to ensure that kernels and hypervisors are not impacted
 107 by userspace ISAMUX/NS mode-switching, it is critical that Supervisor
 108 and Hypervisor modes have their own completely separate ISAMUX/NS SPRs
 109 (imagine a userspace application setting the LE/BE bit on a global basis,
 110 or setting a global IEEE754 FP Standards compatibility flag).
 111
 112 Further, that Supervisor / Hypervisor modes have access to and control
 113 over userspace ISAMUX/NS SPRs (without themselves being affected by
 114 setting *of* userspace ISAMUX/NS SPRs), in order to be able to correctly
 115 context-switch userspace applications to their correct (former) running
 116 state.
 117
 118 Given the number of mode-switch bits that we anticipate using, we advocate
 119 that such a scheme be formalised, and that the OpenPOWER Foundation be
 120 the "atomic arbiter" similar to IANA and JEDEC in the formal allocation
 121 of mode-switch bits to OpenPOWER implementors.
 122
 123 We envisage that some of these bits will be unary, some will be binary,
 124 some will be allocated for exclusive use by the OpenPOWER Foundation,
 125 some allocated to OpenPOWER Members (by the OpenPOWER Foundation),
 126 and some reserved for "custom and experimentation usage".
 127
 128 (This latter - custom experimentation - to be explicitly documented
 129 that upstream compiler and toolchain support will never, under any
 130 circumstances be accepted by the OpenPOWER Foundation, and that this be
 131 enforced through the EULA and through Trademark law).
 132
 133
 134 However as we are quite new to POWER 3.0B (1300+ page PDF), we do
 135 appreciate that such a formal scheme may already be present in POWER9
 136 3.0B, that we have simply overlooked.
 137