3 # Letter regarding ISAMUX / NS
5 This is a quick overview of the way that we would like to add changes
6 that we are proposing to the PowerPC instruction set. It is based on
7 a Open Standardisation of the way that existing "mode switches",
8 already found in the POWER instruction set, are added:
10 * FPSCR's "NI" bit, setting non-IEEE754 FP mode
11 * MSR's "LE" bit (and associated HILE bit), setting little-endian mode
12 * MSR's "SF" bit, setting either 32-bit or 64-bit mode
14 All of these are set by one instruction, that, once set, radically
15 changes the entire behaviour and characteristics of subsequent instructions.
17 With these (and other) long-established precedents already in POWER,
18 there is therefore essentially conceptually nothing new about what we
19 propose: we simply seek that the process by which such "switching" is
20 added is formalised and standardised, such that we (and others) have
21 a clear, standards-non-disruptive, atomic and non-intrusive path to
26 The PowerPC Instruction Set Architecture (ISA) is an abstract model of a
27 computer. This is what programmers use when they write programs for the machine,
28 even if indirectly via a compiler for a high level language. We must be
29 conservative in how we add to the ISA to:
31 * not break existing programs
32 * be mindful as to how others may wish to add to the ISA in the future
34 This document describes our strategy.
37 ## ISA modes and escape sequences
39 New chips usually need to be able to run older (legacy) software that is
40 incompatible with the latest and greatest ISA. Eg: 64 bit chip must be able to
41 run older 16 bit and 32 bit software.
43 To enable backwards compatability the CPU will be set into 'legacy' mode. This
44 is done with an ISA Mode switch, also known as ISA Muxing or ISA Namespaces.
46 The operating system is able to quickly change between 'modern' ISA mode and
49 Another technique is an ISA escape-sequence. This is a type of mode that is
50 only operational for a short time, unlike 32 or 64 bit which would be for the
51 entire run of a program.
54 ## What are we adding to the ISA
56 When high quality graphical display were developed the CPUs at the time were
57 shown to not be able to run the display fast enough. The solution was the use of
58 Graphics cards, these are specialised computers that are good at rendering
59 pixels; often by doing the same thing in different parts of the screen at the
60 same time (in parallel). These specialised computers are called Graphical
61 Processing Units (GPUs).
63 The parallelism of some GPUs is thousands. This has led to GPUs being used to
64 solve non graphical problems where high parallelism is useful.
68 # Letter regarding ISAMUX / NS
70 Hardware-level dynamic ISA Muxing (also known as ISA Namespaces and ISA
71 escape-sequencing) is commonly used in instruction sets, in an arbitrary
72 and ad-hoc fashion, added often on an on-demand basis. Examples include:
74 * Setting a SPR to switch the meaning of certain opcodes for Little-Endian /
75 Big-Endian behaviour (present in POWER and SPARC)
76 * Setting a SPR to provide "backwards-compatibility" for features from
77 older versions of an ISA (such as changing to new ratified versions of
80 (These we term "ISA Muxing" because, ultimately, they are extra bits
81 (or change existing bits) in the actual instruction decoder phase,
82 which involves "MUXes" to switch them on and off).
84 The Libre-SOC team, developing a hybrid CPU-VPU-GPU, needs to add
85 significantly and strategically to the POWER ISA to support, for example,
86 Khronos Vulkan IEEE754 Conformance, whilst *at the same time being able
87 to run full POWER9 compliant instructions*.
89 There is absolutely no way that we are going to duplicate the
90 entire FP opcode set as a custom extension to POWER, just to add a
91 literally-identical suite of FP opcodes that are compliant with the
92 Khronos Conformance Suites: this would be a significant and irresponsible
95 In addition, as this processor is likely to be used for parallel
96 compute purposes in high-efficiency environments, we also need to add
97 FP16 support. Again: there is no way that we are going to add *triple*
98 duplicated opcodes to POWER, given that the opcodes needed are absolutely
99 identical to those that already exist, apart from the FP bitwidth (32
102 There are several other strategically critical uses to which we would
103 like to put such a scheme (related to power consumption and reducing
104 throughput bottlenecks needed for heavy-computation workloads in GPU
107 In addition, the scheme has several other key advantages over other ISA
108 "extending" ideas (such as extending the general ISA POWER space to
109 64 bit) in that, unlike 64 bit opcodes, its judicious and careful use
110 does not require large increases in I-Cache size because all opcodes,
111 ultimately, remain 32-bit. The scheme also allows future *official*
112 POWER extensions to the ISA - managed by the OpenPOWER Foundation -
113 to be strategically managed in a controlled, long-term, non-damaging
114 way to the reputation and stability of OpenPOWER.
116 Therefore we advocate being able to set "ISAMUX/NS" mode-switching bits
117 that, like the *existing* LE/BE mode-switching bits, change the behaviour
118 of *existing* opcodes to an alternative "meaning" (followed by another
119 mode-switch that returns them to their original meaning. Note: to reduce
120 binary code-size, alternative schemes include setting a countdown which,
121 when it expires, automatically disables the requested mode-switch)
123 Note also that to ensure that kernels and hypervisors are not impacted
124 by userspace ISAMUX/NS mode-switching, it is critical that Supervisor
125 and Hypervisor modes have their own completely separate ISAMUX/NS SPRs
126 (imagine a userspace application setting the LE/BE bit on a global basis,
127 or setting a global IEEE754 FP Standards compatibility flag).
129 Further, that Supervisor / Hypervisor modes have access to and control
130 over userspace ISAMUX/NS SPRs (without themselves being affected by
131 setting *of* userspace ISAMUX/NS SPRs), in order to be able to correctly
132 context-switch userspace applications to their correct (former) running
135 Given the number of mode-switch bits that we anticipate using, we advocate
136 that such a scheme be formalised, and that the OpenPOWER Foundation be
137 the "atomic arbiter" similar to IANA and JEDEC in the formal allocation
138 of mode-switch bits to OpenPOWER implementors.
140 We envisage that some of these bits will be unary, some will be binary,
141 some will be allocated for exclusive use by the OpenPOWER Foundation,
142 some allocated to OpenPOWER Members (by the OpenPOWER Foundation),
143 and some reserved for "custom and experimentation usage".
145 (This latter - custom experimentation - to be explicitly documented
146 that upstream compiler and toolchain support will never, under any
147 circumstances be accepted by the OpenPOWER Foundation, and that this be
148 enforced through the EULA and through Trademark law).
151 However as we are quite new to POWER 3.0B (1300+ page PDF), we do
152 appreciate that such a formal scheme may already be present in POWER9
153 3.0B, that we have simply overlooked.