add conversions to appendix
[libreriscv.git] / openpower / sv / int_fp_mv / appendix.mdwn
1 # Equivalent OpenPower ISA v3.0 Assembly Language for FP -> Integer Conversion Modes
2
3 ## Rust
4
5 ```pub fn fcvttgd_rust(v: f64) -> i64 {
6 v as i64
7 }
8
9 pub fn fcvttgud_rust(v: f64) -> u64 {
10 v as u64
11 }
12
13 pub fn fcvttgw_rust(v: f64) -> i32 {
14 v as i32
15 }
16
17 pub fn fcvttguw_rust(v: f64) -> u32 {
18 v as u32
19 }```
20
21 ### 64-bit float -> 64-bit signed integer
22
23 ```
24 .LCPI0_0:
25 .long 0xdf000000
26 .LCPI0_1:
27 .quad 0x43dfffffffffffff
28 example::fcvttgd_rust:
29 .Lfunc_gep0:
30 addis 2, 12, .TOC.-.Lfunc_gep0@ha
31 addi 2, 2, .TOC.-.Lfunc_gep0@l
32 addis 3, 2, .LCPI0_0@toc@ha
33 fctidz 2, 1
34 fcmpu 5, 1, 1
35 li 4, 1
36 li 5, -1
37 lfs 0, .LCPI0_0@toc@l(3)
38 addis 3, 2, .LCPI0_1@toc@ha
39 rldic 4, 4, 63, 0
40 fcmpu 0, 1, 0
41 lfd 0, .LCPI0_1@toc@l(3)
42 stfd 2, -8(1)
43 ld 3, -8(1)
44 fcmpu 1, 1, 0
45 cror 24, 0, 3
46 isel 3, 4, 3, 24
47 rldic 4, 5, 0, 1
48 isel 3, 4, 3, 5
49 isel 3, 0, 3, 23
50 blr
51 .long 0
52 .quad 0
53 ```
54
55 ### 64-bit float -> 64-bit unsigned integer
56
57 ```
58 .LCPI1_0:
59 .long 0x00000000
60 .LCPI1_1:
61 .quad 0x43efffffffffffff
62 example::fcvttgud_rust:
63 .Lfunc_gep1:
64 addis 2, 12, .TOC.-.Lfunc_gep1@ha
65 addi 2, 2, .TOC.-.Lfunc_gep1@l
66 addis 3, 2, .LCPI1_0@toc@ha
67 fctiduz 2, 1
68 li 4, -1
69 lfs 0, .LCPI1_0@toc@l(3)
70 addis 3, 2, .LCPI1_1@toc@ha
71 fcmpu 0, 1, 0
72 lfd 0, .LCPI1_1@toc@l(3)
73 stfd 2, -8(1)
74 ld 3, -8(1)
75 fcmpu 1, 1, 0
76 cror 20, 0, 3
77 isel 3, 0, 3, 20
78 isel 3, 4, 3, 5
79 blr
80 .long 0
81 .quad 0
82 ```
83
84 ### 64-bit float -> 32-bit signed integer
85
86 ```
87 .LCPI2_0:
88 .long 0xcf000000
89 .LCPI2_1:
90 .quad 0x41dfffffffc00000
91 example::fcvttgw_rust:
92 .Lfunc_gep2:
93 addis 2, 12, .TOC.-.Lfunc_gep2@ha
94 addi 2, 2, .TOC.-.Lfunc_gep2@l
95 addis 3, 2, .LCPI2_0@toc@ha
96 fctiwz 2, 1
97 lis 4, -32768
98 lis 5, 32767
99 lfs 0, .LCPI2_0@toc@l(3)
100 addis 3, 2, .LCPI2_1@toc@ha
101 fcmpu 0, 1, 0
102 lfd 0, .LCPI2_1@toc@l(3)
103 addi 3, 1, -4
104 stfiwx 2, 0, 3
105 fcmpu 5, 1, 1
106 lwz 3, -4(1)
107 fcmpu 1, 1, 0
108 cror 24, 0, 3
109 isel 3, 4, 3, 24
110 ori 4, 5, 65535
111 isel 3, 4, 3, 5
112 isel 3, 0, 3, 23
113 blr
114 .long 0
115 .quad 0
116 ```
117
118 ### 64-bit float -> 32-bit unsigned integer
119
120 ```
121 .LCPI3_0:
122 .long 0x00000000
123 .LCPI3_1:
124 .quad 0x41efffffffe00000
125 example::fcvttguw_rust:
126 .Lfunc_gep3:
127 addis 2, 12, .TOC.-.Lfunc_gep3@ha
128 addi 2, 2, .TOC.-.Lfunc_gep3@l
129 addis 3, 2, .LCPI3_0@toc@ha
130 fctiwuz 2, 1
131 li 4, -1
132 lfs 0, .LCPI3_0@toc@l(3)
133 addis 3, 2, .LCPI3_1@toc@ha
134 fcmpu 0, 1, 0
135 lfd 0, .LCPI3_1@toc@l(3)
136 addi 3, 1, -4
137 stfiwx 2, 0, 3
138 lwz 3, -4(1)
139 fcmpu 1, 1, 0
140 cror 20, 0, 3
141 isel 3, 0, 3, 20
142 isel 3, 4, 3, 5
143 blr
144 .long 0
145 .quad 0
146 ```
147
148 ## JavaScript
149
150 ```
151 #include <stdint.h>
152
153 namespace WTF {
154 template<typename Target, typename Src>
155 inline Target bitwise_cast(Src v) {
156 union {
157 Src s;
158 Target t;
159 } u;
160 u.s = v;
161 … if (exp < 32) {
162 int32_t missingOne = 1 << exp;
163 result &= missingOne - 1;
164 result += missingOne;
165 }
166
167 // If the input value was negative (we could test either 'number' or 'bits',
168 // but testing 'bits' is likely faster) invert the result appropriately.
169 return bits < 0 ? -result : result;
170 }
171 ```
172
173 ### 64-bit float -> 32-bit signed integer
174
175 ```
176 toInt32(double):
177 stfd 1,-16(1)
178 li 3,0
179 ori 2,2,0
180 ld 9,-16(1)
181 rldicl 8,9,12,53
182 addi 10,8,-1023
183 cmplwi 7,10,83
184 bgtlr 7
185 cmpwi 7,10,52
186 bgt 7,.L7
187 cmpwi 7,10,31
188 subfic 3,10,52
189 srad 3,9,3
190 extsw 3,3
191 bgt 7,.L4
192 li 8,1
193 slw 10,8,10
194 addi 8,10,-1
195 and 3,8,3
196 add 10,10,3
197 extsw 3,10
198 .L4:
199 cmpdi 7,9,0
200 bgelr 7
201 .L8:
202 neg 3,3
203 extsw 3,3
204 blr
205 .L7:
206 cmpdi 7,9,0
207 addi 3,8,-1075
208 sld 3,9,3
209 extsw 3,3
210 bgelr 7
211 b .L8
212 .long 0
213 .byte 0,9,0,0,0,0,0,0
214 ```