1 # RFC ls006 FPR <-> GPR Move/Conversion
5 * <https://libre-soc.org/openpower/sv/int_fp_mv/>
6 * <https://libre-soc.org/openpower/sv/rfc/ls006.fpintmv/>
7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1015>
8 * <https://git.openpower.foundation/isa/PowerISA/issues/todo>
20 **Books and Section affected**: **UPDATE**
22 * Book I 4.6.5 Floating-Point Move Instructions
23 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
24 * Appendix E Power ISA sorted by opcode
25 * Appendix F Power ISA sorted by version
26 * Appendix G Power ISA sorted by Compliancy Subset
27 * Appendix H Power ISA sorted by mnemonic
31 Single-precision Instructions added:
33 * `fmvtgs` -- Single-Precision Floating Move To GPR
34 * `fmvfgs` -- Single-Precision Floating Move From GPR
35 * `fcvttgs` -- Single-Precision Floating Convert To Integer In GPR
36 * `fcvtfgs` -- Single-Precision Floating Convert From Integer In GPR
38 Identical (except Double-precision) Instructions added:
40 * `fmvtg` -- Double-Precision Floating Move To GPR
41 * `fmvfg` -- Double-Precision Floating Move From GPR
42 * `fcvttg` -- Double-Precision Floating Convert To Integer In GPR
43 * `fcvtfg` -- Double-Precision Floating Convert From Integer In GPR
45 **Submitter**: Luke Leighton (Libre-SOC)
47 **Requester**: Libre-SOC
49 **Impact on processor**:
51 * Addition of four new Single-Precision GPR-FPR-based instructions
52 * Addition of four new Double-Precision GPR-FPR-based instructions
54 **Impact on software**:
56 * Requires support for new instructions in assembler, debuggers,
62 GPR, FPR, Move, Conversion, JavaScript
67 CPUs without VSX/VMX lack a way to efficiently transfer data between
68 FPRs and GPRs, they need to go through memory, this proposal adds more
69 efficient data transfer (both bitwise copy and Integer <-> FP conversion)
70 instructions that transfer directly between FPRs and GPRs without needing
73 IEEE 754 doesn't specify what results are obtained when converting a NaN
74 or out-of-range floating-point value to integer, so different programming
75 languages and ISAs have made different choices. Below is an overview
76 of the different variants, listing the languages and hardware that
77 implements each variant.
79 **Notes and Observations**:
81 * These instructions are present in many other ISAs.
82 * JavaScript rounding as one instruction saves 32 scalar instructions
83 including seven branch instructions.
84 * Both sets are orthogonal (no difference except being Single/Double).
85 This allows IBM to follow the pre-existing precedent of allocating
86 separate Major Opcodes (PO) for Double-precision and Single-precision
91 Add the following entries to:
93 * Book I 4.6.5 Floating-Point Move Instructions
94 * Book I 4.6.7.2 Floating-Point Convert To/From Integer Instructions
95 * Book I 1.6.1 and 1.6.2
101 [[!inline pages="openpower/sv/int_fp_mv/moves_and_conversions" raw=yes ]]
109 # Instruction Formats
111 Add the following entries to Book I 1.6.1.19 XO-FORM:
114 |0 |6 |11 |13 |16 |21 |22 |31 |
115 | PO | RT | IT | CVM | FRB | OE | XO | Rc |
118 Add the following entries to Book I 1.6.1.15 X-FORM:
121 |0 |6 |11 |13 |16 |21 |31 |
122 | PO | FRT | IT | // | RB | XO | Rc |
123 | PO | FRT | // | RB | XO | Rc |
124 | PO | RT | // | FRB | XO | Rc |
129 Add XO to FRB's Formats list in Book I 1.6.2 Word Instruction Fields.
131 Add XO to FRT's Formats list in Book I 1.6.2 Word Instruction Fields.
137 Field used to specify integer type for FPR <-> GPR conversions.
142 Field used to specify conversion mode for
143 integer -> floating-point conversion.
156 Appendix E Power ISA sorted by opcode
157 Appendix F Power ISA sorted by version
158 Appendix G Power ISA sorted by Compliancy Subset
159 Appendix H Power ISA sorted by mnemonic
161 |Form| Book | Page | Version | mnemonic | Description |
162 |----|------|------|---------|----------|-------------|
163 |VA | I | # | 3.2B |todo | |