openpower/sv/rfc/ls007.mdwn

   1 # RFC ls007 Ternary/Binary GPR and CR Field bit-operations
   2
   3 * Funded by NLnet under the Privacy and Enhanced Trust Programme, EU
   4   Horizon2020 Grant 825310, and NGI0 Entrust No 101069594
   5 * <https://libre-soc.org/openpower/sv/bitmanip/>
   6 * <https://libre-soc.org/openpower/sv/rfc/ls007/>
   7 * <https://bugs.libre-soc.org/show_bug.cgi?id=1017>
   8 * <https://git.openpower.foundation/isa/PowerISA/issues/117>
   9
  10 **Severity**: Major
  11
  12 **Status**: new
  13
  14 **Date**: 20 Oct 2022, 1st draft submitted 2023mar22
  15
  16 **Target**: v3.2B
  17
  18 **Source**: v3.1B
  19
  20 **Books and Section affected**: **UPDATE**
  21
  22 * Book I 2.5.1 Condition Register Logical Instructions
  23 * Book I 3.3.13 Fixed-Point Logical Instructions
  24 * Appendix E Power ISA sorted by opcode
  25 * Appendix F Power ISA sorted by version
  26 * Appendix G Power ISA sorted by Compliancy Subset
  27 * Appendix H Power ISA sorted by mnemonic
  28
  29 **Summary**
  30
  31 Instructions added
  32
  33 * `ternlogi` -- GPR Ternary Logic Immediate
  34 * `crternlogi` -- Condition Register Field Ternary Logic Immediate
  35 * `binlog` -- GPR Dynamic Binary Logic
  36 * `crbinlog` -- Condition Register Field Dynamic Binary Logic
  37
  38 **Submitter**: Luke Leighton (Libre-SOC)
  39
  40 **Requester**: Libre-SOC
  41
  42 **Impact on processor**:
  43
  44 * Addition of two new GPR-based instructions
  45 * Addition of two new CR-field-based instructions
  46
  47 **Impact on software**:
  48
  49 * Requires support for new instructions in assembler, debuggers,
  50   and related tools.
  51
  52 **Keywords**:
  53
  54 ```
  55 GPR, CR-Field, bit-manipulation, ternary, binary, dynamic, look-up-table (LUT), FPGA, JIT
  56 ```
  57 **Motivation**
  58
  59 * `ternlogi` is similar to existing `and`/`or`/`xor`/etc. instructions, but
  60   allows any arbitrary 3-input 1-output bitwise operation. This can be used to
  61   combine several instructions into one. E.g. `A ^ (~B & (C | A))` can become
  62   one instruction. This can also be used to have one instruction for
  63   bitwise MUX `(A & B) | (~A & C)`.
  64 * `binlog` is like `ternlogi` except it supports any arbitrary 2-input
  65   1-output bitwise operation, where the operation can be selected dynamically
  66   at runtime. This operates similarly to a LUT in a FPGA.
  67 * `crternlogi` is like `ternlogi` except it works with CRs instead of GPRs.
  68 * `crbinlog` is like `binlog` except it works with CRs instead of GPRs. Likewise it
  69    is similar to a LUT in an FPGA.
  70 * Combined these instructions save on instruction count and also help accelerate
  71   AI and JIT runtimes.
  72
  73 **Notes and Observations**:
  74
  75 * `ternlogi` is like the existing `xxeval` instruction, except operates
  76   on GPRs instead of VSRs and does not require VSX/VMX. SFS and SFFS are
  77   comparatively compromised.
  78 * SVP64/VSX may have different semantics from SVP64/SFFS. SVP64
  79   orthogonality is compromised by a *non*-Vector-considerate argument
  80   that if equivalent  instructions are in VSX they do not have to be
  81   added to SFFS: they do.
  82 * `crternlogi` is similar to the group of CR Operations (crand, cror etc)
  83   which have been identified as a Binary Lookup Group, except an 8-bit
  84   immediate is used instead of a 4-bit one, and up to 4 bits of a CR Field
  85   may be computed at once, saving at least 3 groups of CR operations.
  86 * `crbinlut` is similar to the Binary Lookup Group of CR Operations
  87   except that the 4-bit lookup table comes from a CR Field instead of
  88   from an Immediate. Also like `crternlogi` up to 4 bits may be computed
  89   at once.
  90
  91 **Changes**
  92
  93 Add the following entries to:
  94
  95 * Book I 2.5.1 Condition Register Logical Instructions
  96 * Book I 3.3.13 Fixed-Point Logical Instructions
  97 * Book I 1.6.1 and 1.6.2
  98
  99 ----------------
 100
 101 \newpage{}
 102
 103 [[!inline pages="openpower/sv/tern_bin" raw=yes ]]
 104
 105 # Forms
 106
 107 ## CRB-FORM
 108
 109 Add the following section to Book I 1.6.1
 110
 111 ```
 112
 113     |0   |6   |9    |11   |14   |16   |19   |26  |31   |
 114     | PO | BF | msk | BFA | msk | BFB | TLI | XO | TLI |
 115     | PO | BF | msk | BFA | msk | BFB | //  | XO | /   |
 116 ```
 117
 118 ## TLI-FORM
 119
 120 Add the following section to Book I 1.6.1
 121
 122 ```
 123     |0   |6   |11  |16  |21   |29  |31  |
 124     | PO | RT | RA | RB | TLI | XO | Rc |
 125 ```
 126
 127 ## VA-FORM
 128
 129 Add the following entry to VA-FORM in Book I 1.6.1.12
 130
 131 ```
 132     |0      |6     |11     |16     |21     |26|27   |
 133     | PO    |  RT  |   RA  |   RB  |    RC |nh| XO  |
 134 ```
 135
 136 ## Word Instruction Fields
 137
 138 Add the following to Book I 1.6.2
 139
 140 ```
 141 msk (9:10,14:15)
 142     Field used by crternlogi and crbinlut to decide which CR Field bits to
 143     modify.
 144     Formats: CRB
 145 nh (26)
 146     Nibble High. Field used by binlog to decide if the look-up-table should
 147     be taken from bits 60:63 (nh=0) or 56:59 (nh=1) of RC.
 148     Formats: VA
 149 TLI (21:28)
 150     Field used by the ternlogi instruction as the
 151     look-up table.
 152     Formats: TLI
 153 TLI (21:25,19:20,31)
 154      Field used by the crternlogi instruction as the
 155      look-up table.
 156      Formats: CRB
 157 ```
 158
 159 * Add `TLI` to the `Formats:` list of all of `RA`, `RB`, `RT`, and `Rc`.
 160 * Add `CRB` to the `Formats:` list of all of `BF`, `BFA`, `BFB`, and `BFC`.
 161 * Add `TLI` to the `Formats:` list of `XO (29:30)`.
 162 * Add `CRB` to the  `Formats:` list of `XO (26:31)`.
 163 * Add `VA` to the  `Formats:` list of `XO (27:31)`.
 164
 165 ----------
 166
 167 # Appendices
 168
 169     Appendix E Power ISA sorted by opcode
 170     Appendix F Power ISA sorted by version
 171     Appendix G Power ISA sorted by Compliancy Subset
 172     Appendix H Power ISA sorted by mnemonic
 173
 174 |Form| Book | Page | Version | mnemonic   | Description |
 175 |----|------|------|---------|------------|-------------|
 176 |TLI | I    | #    | 3.2B    | ternlogi   | GPR Ternary Logic Immediate |
 177 |VA  | I    | #    | 3.2B    | binlog     | GPR Binary Logic            |
 178 |CRB | I    | #    | 3.2B    | crternlogi | CR Field Ternary Logic Immediate |
 179 |CRB | I    | #    | 3.2B    | crbinlog   | CR Field Binary Logic |
 180
 181 [[!tag opf_rfc]]
 182
 183 ----------------
 184