# 180 nm ASIC plan for Oct 2020

NOTE: moved to Jun 9th 2021 (sigh should not have put a date in the page name, oh well)

This page is for discussion of what we can aim for and reasonably achieve.
To be expanded with links to bugreports

Links:

* <https://gitlab.com/Chips4Makers>
* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/007699.html>

## Minimum viability

* a Wishbone interface.  this allows us to drop *directly* into
  already-written Litex "SOC" infrastructure (leaving all of us free to
  focus on the essentials)
* the dependency matrices are essential.
* a Branch Function Unit is essential (minimum of 1)
* Load/Store Function Units are essential
* so are multiple register file files (SPRs, Condition Regs, 32x INT Regs)
* the integer pipelines (integer and logic instructions) are essential
  (the FP ones not so much)
  <https://bugs.libre-soc.org/show_bug.cgi?id=305>
* a very very basic Branch Prediction system (fixed, but observing POWER
  branch "hints")
* a very very basic Common Data Bus infrastructure.
* a TLB and MMU are not strictly essential (not for a proof-of-concept ASIC)
* neither in some ways is a L1 cache
* [[180nm_Oct2020/interfaces]] we need as a bare minimum include JTAG,
  GPIO, EINT, SPI and QSPI, I2C, UART16550, LPC (from Raptor Engineering)
  and that actually might even be it.
* [[180nm_Oct2020/ls180]] actual auto-generated pinouts by pinmux program

## Secondary priorities

* a PLL (this is quite a lot however it turns the ASIC from a 24mhz
  design into a 300mhz design)
* a TLB and MMU (in combination with a PLL if it is GNU/Linux OS capable
  we have an actual viable *saleable product*, immediately)
* dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
* multiple Common Data Buses to / from the RegFile along with a 4x
  "Striped" HI/LO-32-ODD/EVEN access pattern.
* multi-issue
* PartitionedSignal-based integer pipelines
* an FP regfile and associated FP pipelines
* SV compliance
* 128x INT/FP registers
* GPU-style opcodes - Jacob mentioned Texturisation opcodes as being
  more important than e.g. SIN/COS.
* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII, SD/MMC,
  USB-ULPI
* a pinmux
* [FSI instead of JTAG](https://gitlab.raptorengineering.com/raptor-engineering-public/lpc-spi-bridge-fpga/-/blob/master/fsi_master.v)

# Available people

* Rudi from <http://asics.ws> to cover the interface set
* [[lkcl]] for the scoreboard systems
* [[programmerjake]] TODO
* [[tplaten]] memory and cache
* [[jock_tanner]] TODO
* MarketNext TODO

# Preliminary coriolis2 ASIC layout

## 02jul2020 - first version

* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-July/008438.html>

[[!img 180nm_Oct2020/2020-07-02_19-01.png size="900x" ]]

## 03jul2020 - DIV unit added

[[!img 180nm_Oct2020/2020-07-03_11-04.png size="900x" ]]

## 28dec2020 - End of year progress update

### With blockage layers

[[!img 180nm_Oct2020/2020-12-28.png size="900x" ]]

### Without blockage layers so wires can be seen more clearly

[[!img 180nm_Oct2020/2020-12-28_without_blockages.png size="900x" ]]