# Cesar Strauss

Contributor

* [Bugtracker assignments](https://bugs.libre-soc.org/buglist.cgi?email1=cestrauss@gmail.com&emailassigned_to1=1&emailcc1=1&emailtype1=substring&resolution=---)

# Status Tracking

## Currently working on

1. ALU CompUnit needs to recognise that RA (src1) can be zero  
	<https://bugs.libre-soc.org/show_bug.cgi?id=336>  
	Status: DONE  
	Unit test Status: in progress


2. Something about the above (5), being optional.  
	<https://bugs.libre-soc.org/show_bug.cgi?id=336#c5>  
	Status: DONE  
	Unit test Status: in progress

3. CompALUMulti parallel functions unit test  
	<https://bugs.libre-soc.org/show_bug.cgi?id=336#c11>  
	Priority: Medium-to-High

4. Code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU  
	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c18>  
	Status: Need a review of Luke's implementation, compared to mine.  
	Priority: Low

5. Test dual ports (two L0CacheBuffer with two ports, 4-4 as well) which
write to the same memory  
	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c11>  
	Status: not started  
	Priority: High

6. Luke tried two LDs in the score6600 code - they failed.  
	<https://bugs.libre-soc.org/show_bug.cgi?id=318#c17>  
	Status: not started, need to check the [prototype] L0CacheBuffer  
	Priority: High

7. Fix a bug in the LDSTCompUnit  
	<https://bugs.libre-soc.org/show_bug.cgi?id=318>  
	Status: Luke thinks he fixed it, but needs a review and improving the
unit tests.   
	See: <https://bugs.libre-soc.org/show_bug.cgi?id=318#c7>  
	Priority: Medium

8. LDSTCompUnit parallel functions unit test  
	<https://bugs.libre-soc.org/show_bug.cgi?id=350>  
	Priority: Medium-ish

11. Formal Proof for CompUnit  
        <https://bugs.libre-soc.org/show_bug.cgi?id=342>

12. Formal Proof for PartitionedSignal  
        <https://bugs.libre-soc.org/show_bug.cgi?id=565>  
        Status: in progress  

13. Implement simple VL for-loop in nMigen for TestIssuer  
        <https://bugs.libre-soc.org/show_bug.cgi?id=583>  
        Status: in progress  

## Completed but not yet submitted:

1. FSM-based ALU example needed (compliant with ALU CompUnit)  
	<https://bugs.libre-soc.org/show_bug.cgi?id=417>  

2. Fix MSB0 issues in the SVP64 Assembler, Simulator and Decoder  
	<https://bugs.libre-soc.org/show_bug.cgi?id=600>

## Submitted for NLNet RFP

### NLnet.2019.02.012

* [Bug #583](https://bugs.libre-soc.org/show_bug.cgi?id=583):
  Implement simple VL for\-loop in nMigen for TestIssuer
    * &euro;2325 which is the total amount
    * submitted on 2022-06-16

### NLNet.2019.10.032.Formal

* [Bug #565](https://bugs.libre-soc.org/show_bug.cgi?id=565):
  Improve formal verification on PartitionedSignal
    * &euro;2200 out of total of &euro;3000
    * submitted on 2022-06-16

### NLNet.2019.10.046.Standards

* [Bug #588](https://bugs.libre-soc.org/show_bug.cgi?id=588):
  add SVP64 to PowerDecoder2
    * &euro;300 out of total of &euro;1000
    * submitted on 2022-06-16

## Paid

### NLNet.2019.10.043.Wishbone

* [Bug #475](https://bugs.libre-soc.org/show_bug.cgi?id=475):
  cxxsim improvements
    * Ran several Libre-SOC tests under cxxsim
    * Helped isolate simulator issues by extracting a MVCE
(Minimal, Verifiable, Complete Example) in each case.
    * paid on 2021-05-11
    * &euro;250 out of total of &euro;1750