# LLVM Backend Array Register Files

This backend is for expressing scenarios where registers have multiple
potential overlapping meanings and uses, including but not limited to:

* **MMX / SSE / SIMD**: same registers of fixed length can be subdivided into
  multiple different SIMD elements, depending on the opcode used (or
  special CSRs - Control Status Registers)
* **Virtual register redirection**: setting a CSR changes
  the meaning of instruction opcodes to access different "banks".
* **Special register types**: expression of special register types,
  not just integer and float, but shader types for use in 3D, or
  Galois Field (GF).
* Variations and combinations of the above

# Data Structures

## Array Register File

This is for being able to express remapping / retargetting / redirection
schemes that a microarchitecture has.

    typedef struct {
        start: 12; // starting index of the "register"
        end: 12; // ending index of the "register" (inclusive)
        id: 8; // type of register: e.g 0=float, 1=int, 2=...
    } ARF;

Examples:

    ARF1 = 0x01009005
    ARF2 = 0x0100a006
    ARF3 = 0x0100b008

These would indicate that when the (virtual) register ARF1 is used,
it is of type "integer", and it requires the reservation of the **real**
registers 5 through 9 at the hardware level.

## Base Register Class

    typedef struct {
        ARF: arf;  // the Array Register File identifier
        min: 12;   // if an opcode restricts the available range, use this
        max: 12;   // ... and this
        size: 8;   // the element bitwidth. e.g. 0=8, 1=16, 2=32.. TBD
        align: 4;  // an aligment restriction, in powers of 2.
    } BRC;

Examples:

    A Compressed instruction from SV has restrictions on the
    range it may cover (unless redirection is taken into account).
    It is also possible to specify a bitwidth of 16, and if that is
    done, alignment has to be restricted to 4.  So:

    brc1 = {
        arf = 0x0100b008; // integer register, using "real" regs 8-11 inclusive
        min = 8;          // C-type instructions go from 8-15 in the opcode
        max = 15;
        size = 0x1        // 1=16-bit (?)
        align: 2          // 2= 1<<2 (=4) because the "real" regs are 64-bit.
    };

## Register Class Unions

Register Classes are the union of multiple Base Register Classes
and traditional register classes.  In this way, all possible meanings
and uses to which registers may be put can be expressed in one structure.

# Examples per Implementor

## Array Register File

### SimpleV

### AMDGPU

## Base Register Class

### SimpleV

### AMDGPU

## Register Class Unions

### SimpleV

### AMDGPU