# Lanes
+Register table
+
+| reg num | Lane 0 | Lane 1 | Lane 2 | Lane 3 |
+| ------- | ------ | ------ | ------ | ------ |
+| r0 | (31.0) | (31.0) | (31.0) | (31.0) |
+| r1 | (31.0) | (31.0) | (31.0) | (31.0) |
+| r2 | (31.0) | (31.0) | (31.0) | (31.0) |
+
Example parallel add:
/* XLEN and N are "baked-in" to the hardware */