+# OpenPOWER
+
+In the late 1980s [[!wikipedia IBM]] developed a POWER family of processors.
+This evolved to a specification known as the POWER ISA. In 2019 IBM made the POWER ISA [[!wikipedia Open_source]], to be looked after by the existing [[!wikipedia OpenPOWER_Foundation]]. Here is a longer history of [[!wikipedia IBM_POWER_microprocessors]]. These IBM proprietary processors
+happen to implement what is now known as the POWER ISA. The names
+POWER8, POWER9, POWER10 etc. are product designations equivalent to Intel
+i5, i7, i9 etc. and are frequently conflated with versions of the POWER ISA (v2.07, v3.0c, v3.1b).
+
+Libre-SOC is basing its [[Simple-V Vectorisation|sv]] CPU extensions on POWER ISA, because it wants to be able to specify a machine that can be completely trusted, and because POWER, thanks to IBM's involvement,
+is designed for high performance.
+
+See wikipedia page
+<https://en.m.wikipedia.org/wiki/Power_ISA>
+
+very useful resource describing all assembly instructions
+<https://www.ibm.com/docs/en/aix/7.1?topic=reference-instruction-set>
+
# Evaluation
EULA released! looks good.
+<https://openpowerfoundation.org/final-draft-of-the-power-isa-eula-released/>
-Links
+# Links
+* OpenPOWER Membership
+ <https://openpowerfoundation.org/join/>
* OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
* [[openpower/isatables]]
+* [[openpower/whitepapers]]
* [[openpower/isa]] - pseudo-code extracted from POWER V3.0B PDF spec
* [[openpower/gem5]]
+* [[openpower/sv]]
+* [[openpower/prefix_codes]] Decode/encode prefix-codes, used by JPEG, DEFLATE, etc.
+* [[openpower/opcode_regs_deduped]]
+* [[openpower/simd_vsx]]
+* [[openpower/ISA_WG]] - OpenPOWER ISA Working Group
* [[openpower/pearpc]]
* [[openpower/pipeline_operands]] - the allocation of operands on each pipeline
* [[3d_gpu/architecture/decoder]]
* Opcode 4 Signal Processing (SPE)
* Opcode 4 Vectors or Opcode 60 VSX (600+ additional instructions)
* Avoidable legacy opcodes
+* SIMD. it's awful.
# SimpleV
-see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
+see [[openpower/sv]].
SimpleV: a "hardware for-loop" which involves type-casting (both) the
register files to "a sequence of elements". The **one** instruction
(an unmodified **scalar** instruction) is interpreted as a *hardware
saving hugely on both hardware and compiler development time when
the concept is dropped on top of a pre-existing ISA.
-## Condition Registers
-
-Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1. When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
-
-## Carry
-
-SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
-
# Integer Overflow / Saturate
Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE). To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
-# RISCV userspace
-
-Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
-
-the exception entry point:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409>
-
-the rest of the context switch code is in a different file:
-<https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589>
projects / libreriscv.git / blobdiff