zeroing set to 0

[libreriscv.git] / simple_v_extension.mdwn

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index 6ce30addeda44a4e57ad61aa492bc42005be7051..ea10abce962bf2cd7aa22babf8697d96ada5a3e2 100644 (file)
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -416,7 +416,7 @@ integer registers (as a future option)
   register itself.
 * zeroing is either 1 or 0, and if set to 1, the operation must
   place zeros in any element position where the predication mask is
-  set to zero.  If zeroing is set to 1, unpredicated elements *must*
+  set to zero.  If zeroing is set to 0, unpredicated elements *must*
   be left alone.  Some microarchitectures may choose to interpret
   this as skipping the operation entirely.  Others which wish to
   stick more closely to a SIMD architecture may choose instead to