Fixed embedded images

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index 018a41fa23a63061cfd141098b8c3c9a3c01a218..4a91b755493a1aca82de29c6e2b3afff9f40e679 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -413,11 +413,11 @@ there will be a lag on the output data compared to the incoming
 
 [[!img gpio_block.png]]
 
-[[!img io_mux_bank_planning.JPG]]
+[[!img io_mux_bank_planning.JPG size="600px"]]
 
 # Core/Pad Connection + JTAG Mux
 
 Diagram constructed from the nmigen plat.py file.
 
-[[!img i_o_io_tristate_jtag.JPG]]
+[[!img i_o_io_tristate_jtag.JPG size="600x"]]
 

diff --git a/docs/pinmux/temp_pinmux_info.mdwn b/docs/pinmux/temp_pinmux_info.mdwn
index 2f417b35d8b1e2acd5ab5fb0a8d4f3d8888211f7..596c5ec2ce1ec2502e1609a7e7fae9a78c329226 100644 (file)
--- a/docs/pinmux/temp_pinmux_info.mdwn
+++ b/docs/pinmux/temp_pinmux_info.mdwn
@@ -134,7 +134,7 @@ the signals are correct.
 
 # Pinmux GPIO Block
 ## Diagram
-[[!img banked_gpio_block.png size="600x"]]
+[[!img banked_gpio_block.jpg size="600x"]]
 
 ## Explanation
 The simple GPIO module is multi-GPIO block integral to the pinmux system.
@@ -181,7 +181,7 @@ state of the configuration as part of the code (essentially a shadow register).
 The diagram below shows the layout of the configuration byte, and how it fits
 within a 64-bit data word. 
 
-[[!img gpio_csr_example.png size="600x"]]
+[[!img gpio_csr_example.jpg size="600x"]]
 
 If the block is created with more GPIOs than can fit in a single data word, 
 the next set of GPIOs can be accessed by incrementing the address.
@@ -190,7 +190,7 @@ For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs
 (TODO: DOES ADDRESS COUNT WORDS OR BYTES?)
 
 ## Example Memory Map
-[[!img gpio_memory_example.png size="600x"]]
+[[!img gpio_memory_example.jpg size="600x"]]
 
 The diagrams above show the difference in memory layout between 16-GPIO block implemented with 64-bit and 32-bit WB data buses. The 64-bit case shows there are two rows with eight GPIOs in each, and it will take two writes (assuming simple WB write) to completely configure all 16 GPIOs. The 32-bit on the other hand has four address rows, and so will take four write transactions.