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diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index f2104937115dac5129fc14162b289438f9be5d31..ec39b41b0464a035fb78ff2ae41b55b82f6fcace 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -113,6 +113,10 @@ This includes adding DMI get/set support in hardware as well as gdb (remote) sup
 * power-gem5 remote gdb: TODO
 * TestIssuer: TODO
 
+Links:
+
+* <https://bugs.libre-soc.org/show_bug.cgi?id=609>
+
 ## sv.setvl
 
 a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. primarily the `SVSTATE` SPR.  the dual-access SPRs for VL and MVL which mirror into the SVSTATE.VL and SVSTATE.MVL fields are not immediately essential to implement.
@@ -123,6 +127,8 @@ a [[sv/setvl]] instruction is needed, which also implements [[sv/sprs]] i.e. pri
 * TestIssuer: TODO
 * Microwatt: TODO
 
+Links:
+
 ## SVSRR0 for exceptions
 
 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).