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diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index e390b4aa149443f123194dc394022f53841e3f7c..99c31b29677054e4cc2f4238907a2f6f601bef2a 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -42,7 +42,11 @@ Next we will wire up the STLINKv2 and our FPGA in three separate stages.
 
 * First attaching one end of a jumper cable to each necessary header pin on the STLINKv2. 
 
-* Then we will attach the end of a new jumper cable to each male header pin on the FPGA. Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires. This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
+* Then we will attach the end of a new jumper cable to each male header pin on the FPGA.
+
+* Finally, we will connect the wires from the STLINKv2 to the wires from the FPGA by matching the colours of the wires.
+
+This way you do not lose the connections when you want to disconnect and store the two devices. We are using FEMALE-TO-FEMALE jumper cables on the male header pins of each of the FPGA so that the wires do not randomly damage the bare PCB due to a short.
 
 We will wire each of the pins on the the STLINKv2 according to the diagrams, tables, and images on this page.