powerpc-add/src/glossary.tex

   1 % Glossary
   2
   3 % In the main documentation text I have not tagged every use of the glossary
   4 % entries below, I have tagged the first in a chapter, or first use for some
   5 % number of paragraphs.
   6
   7 % Put the definition of terms of the glossary terms in here
   8 % Try to keep in alphabetic order - for easier editing, they will
   9 % be generated (in the PDF) in alphabetic order regardless of the order below
  10
  11 % To use one do something like: \gls{PowerPC}
  12 % Note that the entries are case sensitive.
  13
  14 % Having an entry below will not make it appear in the glossary,
  15 % it will only appear if it is used, eg: \gls{PowerPC}
  16
  17 % How to use:
  18 % GlsName       The text that should be used in the document, eg: \gls{GlsName}
  19 % GlsText       The text that will be shown in the document in place of \gls{GlsName}
  20 %               GlsName and GlsText can be different but you will probably want
  21 %               to make them the same.
  22 % \newglossaryentry{GlsName}
  23 % {
  24 %   name=GlsText,
  25 %   description={
  26 %     See: \href{}{}
  27 %     }
  28 % }
  29
  30 % See:
  31 % https://en.wikibooks.org/wiki/LaTeX/Glossary
  32 % http://tug.ctan.org/macros/latex/contrib/glossaries/glossariesbegin.pdf
  33
  34 % An empty entry to use as a template:
  35 % \newglossaryentry{}
  36 % {
  37 %   name=,
  38 %   description={
  39 %     See: \href{}{}
  40 %     }
  41 % }
  42
  43 % BUG: the glossary entries have a '.' after them that I am not expecting.
  44
  45 % BEWARE: the documentation may need to be built more than once for all of the
  46 % entries below to appear. This seems to be if an entry is only mentioned in another
  47 % glossary entry.
  48
  49 \newglossaryentry{Binutils}
  50 {
  51   name=Binutils,
  52   description={
  53     GNU Binary Utilities is part of the toolchain used for creating and managing
  54     binary objects (compiled code).
  55     Used with \gls{gcc}.
  56     See: \href{https://www.gnu.org/software/binutils/}{GNU web site}
  57     }
  58 }
  59
  60 \newglossaryentry{CPU}
  61 {
  62   name=CPU,
  63   description={
  64     Central Processing Unit.
  65     The brain of a conventional computer that executes general purpose programs.
  66     Contrast with \gls{GPU} and \gls{VPU}.
  67 %    See: \href{}{}
  68     }
  69 }
  70
  71 \newglossaryentry{CSR}
  72 {
  73   name=CSR,
  74   description={
  75      Control and Status Register.
  76      A special register that records CPU status and processing options.
  77      One important option to this project is that the special instructions
  78      that we have created will be recognised.
  79 %    See: \href{}{}
  80     }
  81 }
  82
  83 \newglossaryentry{FPGA}
  84 {
  85   name=FPGA,
  86   description={
  87     Field-programmable gate array.
  88     An integrated circuit where the circuitry can be reconfigured.
  89     See: \href{https://en.wikipedia.org/wiki/Field-programmable_gate_array}{Wikipedia}
  90     }
  91 }
  92
  93 \newglossaryentry{gcc}
  94 {
  95   name=gcc,
  96   description={
  97     \gls{GNU} Compiler Collection.
  98     A popular open source compiler for C (\& related), Fortran, Ada \& Go and able to generate
  99     object code for many \gls{ISA}s including \gls{PowerPC}.
 100     See: \href{https://en.wikipedia.org/wiki/GNU_Compiler_Collection}{Wikipedia}
 101     }
 102 }
 103
 104
 105 \newglossaryentry{GNU}
 106 {
 107   name=GNU,
 108   description={
 109     The GNU project is a large collection of free software.
 110     It provides many of the core programs that are used by many \gls{Linux} distributions.
 111     See: \href{https://www.gnu.org/}{GNU website}
 112     }
 113 }
 114
 115 \newglossaryentry{GPU}
 116 {
 117   name=GPU,
 118   description={
 119     Graphics processing unit.
 120     Special purpose processor optimised for graphics and image generation,
 121     often able to run in parallel -- the same instructions on
 122     different data at the same time.
 123     Contrast with \gls{CPU} and \gls{VPU}.
 124     See: \href{https://en.wikipedia.org/wiki/Graphics_processing_unit}{Wikipedia}
 125     }
 126 }
 127
 128 \newglossaryentry{ICubeCorpIC3128}
 129 {
 130   name=ICubeCorp IC3128,
 131   description={
 132     A \gls{SoC} from ICube that has both \gls{CPU} and \gls{GPU} on a single chip.
 133     See: \href{https://www.cnx-software.com/2014/10/15/icube-mvp-socs-combine-cpu-and-gpu-into-a-single-unified-processing-unit-upu/}{CNX Software}
 134     }
 135 }
 136
 137 \newglossaryentry{IEEE754}
 138 {
 139   name=IEEE754,
 140   description={
 141     A popular standard way of representing and manipulating floating point numbers.
 142     Initiated by the  Institute of Electrical and Electronics Engineers in 1985.
 143     Different precisions from 16 to 256 bits are described.
 144     See: \href{https://en.wikipedia.org/wiki/IEEE_754}{Wikipedia}
 145     }
 146 }
 147
 148 \newglossaryentry{IOMMU}
 149 {
 150   name=IOMMU,
 151   description={
 152     Input Output Memory Management Unit.
 153     Mediates between Input/Output devices and main memory mapping virtual
 154     addresses to physical ones and, maybe, enforcing protection restrictions.
 155     See: \href{https://en.wikipedia.org/wiki/Input%E2%80%93output_memory_management_unit}{Wikipedia}
 156     }
 157 }
 158
 159 \newglossaryentry{ISA}
 160 {
 161   name=ISA,
 162   description={
 163     Instruction Set Architecture.
 164     An abstract model of a computer a definition that includes: registers, memory access,
 165     input/output, data types, CPU instruction set.
 166     Everything that is needed to be able to create programs to run on the machine.
 167     See: \href{https://en.wikipedia.org/wiki/Instruction_set_architecture}{Wikipedia}
 168     }
 169 }
 170
 171 \newglossaryentry{ISAMUX}
 172 {
 173   name=ISAMUX,
 174   description={
 175     \gls{ISA} \gls{MUX} -- having the same bits in the ISA mean different things.
 176     }
 177 }
 178
 179 \newglossaryentry{H.265}
 180 {
 181   name=H.265,
 182   description={
 183     High Efficiency Video Coding, also known as HEVC \& MPEG-H Part 2.
 184     Released in 2013.
 185     Its data compression is better, for the same video quality, than previous standards:
 186     AVC, H.264, or MPEG-4 Part 10.
 187     Patent license may be required for H.265 use.
 188     See: \gls{VP9}
 189     \href{https://en.wikipedia.org/wiki/High_Efficiency_Video_Coding}{Wikipedia}
 190     }
 191 }
 192
 193 \newglossaryentry{JIT}
 194 {
 195   name=JIT,
 196   description={
 197     Just In Time compilation.
 198     Translate when the program runs, only when needed.
 199     See: \href{https://en.wikipedia.org/wiki/Just-in-time_compilation}{Wikipedia}
 200     }
 201 }
 202
 203 \newglossaryentry{Linux}
 204 {
 205   name=Linux,
 206   description={
 207     A free kernel on which free operating systems and specialised environments are built.
 208     Linux is found all the way for small, embedded systems, to desktops, to servers
 209     and the world's biggest super computers.
 210     It runs on many \gls{ISA}s and supports a huge variety of peripheral devices.
 211     Linux was inspired by Unix and is upwards compatible with POSIX.
 212     See: \href{https://www.linuxfoundation.org/}{Linux Foundation}
 213     }
 214 }
 215
 216
 217 \newglossaryentry{LLVM}
 218 {
 219   name=LLVM,
 220   description={
 221     A compiler and related toolchain.
 222     An open source and able to compileAda, C, C++, D, Delphi, Fortran, Haskell, Julia, Objective-C, Rust, and Swift
 223     able to generate object code for many \gls{ISA}s including \gls{PowerPC}.
 224     See: \href{https://en.wikipedia.org/wiki/LLVM}{Wikipedia}
 225     }
 226 }
 227
 228 \newglossaryentry{MISA}
 229 {
 230   name=MISA,
 231   description={
 232     Multiple Instruction Sets Architecture.
 233     The ability to run more than one \gls{ISA} on the same hardware.
 234     A setting in a \gls{CSR} controls which instructions will be
 235     recognised at any time.
 236     See: \href{}{}
 237     }
 238 }
 239 % https://ieeexplore.ieee.org/document/6136696 - paywalled
 240 % https://www.researchgate.net/figure/Overview-of-the-MISA-instructional-system-design-method_fig2_245165034
 241 % https://people.eecs.berkeley.edu/~krste/papers/riscv-privileged-v1.9.pdf page 15
 242
 243 \newglossaryentry{MUX}
 244 {
 245   name=MUX,
 246   description={
 247     Multiplex, a way of compressing several things into the same data.
 248 %    See: \href{}{}
 249     }
 250 }
 251
 252 \newglossaryentry{PowerPC}
 253 {
 254   name=PowerPC,
 255   description={
 256     A \gls{RISC} \gls{ISA} created in 1991 by Apple, IBM and Motorola.
 257     The name is a backronym: Performance Optimization With Enhanced RISC
 258     Performance Computing, sometimes abbreviated as PPC or called POWER).
 259     See: \href{https://en.wikipedia.org/wiki/PowerPC}{Wikipedia}
 260   }
 261 }
 262
 263 \newglossaryentry{RISC}
 264 {
 265   name=RISC,
 266   description={
 267     Reduced Instruction Set Computer.
 268     A computer design philosophy that features simple but fast instructions,
 269     often with many registers.
 270     See: \href{https://en.wikipedia.org/wiki/Reduced_instruction_set_computer}{Wikipedia}
 271     }
 272 }
 273
 274 \newglossaryentry{RISCV}
 275 {
 276   name=RISC-V,
 277   description={
 278     An open sourced \gls{RISC} \gls{ISA} started in 2010 at the University of California, Berkeley.
 279     See: \href{https://en.wikipedia.org/wiki/RISC-V}{Wikipedia}
 280     }
 281 }
 282
 283 \newglossaryentry{SoC}
 284 {
 285   name=SoC,
 286   description={
 287     System on a Chip.
 288     An integrated circuit that has (almost all) the components needed to
 289     make a fully running system.
 290     See: \href{https://en.wikipedia.org/wiki/System_on_a_chip}{Wikipedia}
 291     }
 292 }
 293
 294 \newglossaryentry{SPARC}
 295 {
 296   name=SPARC,
 297   description={
 298     A \gls{RISC} \gls{ISA} created by Sun Microsystems.
 299     See: \href{https://en.wikipedia.org/wiki/SPARC}{Wikipedia}
 300     }
 301 }
 302
 303 \newglossaryentry{SupervisorMode}
 304 {
 305   name=Supervisor Mode,
 306   description={
 307     A privileged CPU state where the program can execute instructions or otherwise
 308     do things that a non-privileged program would not be allowed to do.
 309 %    See: \href{}{}
 310     }
 311 }
 312
 313 \newglossaryentry{VideoCoreIV}
 314 {
 315   name=VideoCore IV,
 316   description={
 317     Low power \gls{SoC} from Broadcom. ARM CPU that is used in the Raspberry Pi.
 318     See: \href{https://en.wikipedia.org/wiki/VideoCore}{Wikipedia}
 319     }
 320 }
 321
 322 \newglossaryentry{VP9}
 323 {
 324   name=VP9,
 325   description={
 326     Video encoding format released by Google in 2013.
 327     Released open \& royalty free although Sisvel has made some claims.
 328     See: \href{https://en.wikipedia.org/wiki/VP9}{Wikipedia}
 329     }
 330 }
 331
 332 % https://libre-soc.org/vpu/
 333 \newglossaryentry{VPU}
 334 {
 335   name=VPU,
 336   description={
 337      Video Processing Unit.
 338      Similar to a \gls{CPU} but has extra hardware instructions to speed up things
 339      like the decoding and encoding of \gls{H.265}, or \gls{VP9}.
 340 %    See: \href{}{}
 341     }
 342 }
 343
 344 \newglossaryentry{Z80}
 345 {
 346   name=Zilog Z80,
 347   description={
 348     An 8 bit processor produced by the Zilog Inc in 1986.
 349     It is compatible with the Intel 8080 processor.
 350     See: \href{https://en.wikipedia.org/wiki/Z80}{Wikiedia}
 351     }
 352 }
 353
 354 % Other entries to consider:
 355 % emulator
 356 % namespace
 357 % MSB
 358 % PCR
 359 % SIMD
 360 % ALU
 361 % RA
 362 % RB
 363 % microwatt     https://github.com/antonblanchard/microwatt/blob/master/decode1.vhdl
 364 % 6600          https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
 365 % DAG           Directed Acyclic Graph
 366 % SR latch
 367 % FU            Functional Unit
 368 % FPU           float point unit
 369 % WAR           https://libre-soc.org/3d_gpu/architecture/6600scoreboard/ #10
 370 % ALU
 371 % FU-FU function to function    https://libre-soc.org/3d_gpu/architecture/6600scoreboard/       #14
 372 % GORD GOWR     GO read/write
 373 % ISANS
 374 %  Unified Processing Unit (UPU)
 375 %  MVP (Multi-thread Virtual Pipeline
 376 % SIE
 377 % WARL
 378 % WLRL