7 A fixed number of additional (hidden) bits, conceptually a
\textbf{namespace
},
8 set by way of a CSR or other out-of-band mechanism,
9 that go directly and non-optionally
10 into the instruction decode phase, extending (in each implementation) the
11 opcode length to
16+N,
32+N,
48+N, where N is a hard fixed quantity on
12 a per-implementor basis.
16 Where the opcode is normally loaded from the location at the PC, the extra
17 bits, set via a CSR, are mandatorially appended to every instruction: hence why
18 they are described as "hidden" opcode bits, and as a
\textbf{namespace
}.
22 The parallels with c++
\textbf{using namespace
} are direct and clear.
23 Alternative conceptual ways to understand this concept include
24 \textbf{escape-sequencing
}.
28 TODO: reserve some bits which permit the namespace
\textbf{escape-sequence
} to
29 be relevant for a fixed number of instructions at a time. Caveat:
30 allowing such a countdown to cross branch-points is unwise (illegal
35 An example of a pre-existing
\textbf{namespace
} switch that has been in
36 prevalent use for several decades (SPARC and other architectures):
37 dynamic runtime selectability of littel-endian / big-endian
\textbf{meaning
}
38 of instructions by way of a
\textbf{mode switch
} instruction (of some kind).
42 That
\textbf{switch
} is in effect a
33rd (hidden) bit that is part of the opcode,
43 going directly into the mux / decode phase of instruction decode, and
44 thus qualifies categorically as a
\textbf{namespace
}. This proposal both formalises
45 and generalises that concept.
47 \section{Hypothetical Format
} \label{hypotheticalformat
}
51 Note that this is a hypothetical format, yet TBD, where particular attention
52 needs to be paid to the fact that there is an
\textbf{immediate
} version of CSRRW
53 (with
5 bits of immediate) that could save a lot of space in binaries.
57 |
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0|
58 |------------------------------ |-------|---------------------|-|
59 |
1 custom custom custom custom custom | foreignarch |
1|
60 |
0 reserved reserved reserved reserved reserved | foreignarch |
1|
61 |custom | reserved | official|B| rvcpage |
0|
74 when bit
0 is
0,
\textbf{RV
} mode is selected.
78 in RV mode, bits
1 thru
5 provide up to
16 possible alternative meanings
79 (namespaces) for
16 Bit opcodes.
\textbf{pages
} if you will. The top bit
80 indicates custom meanings. When set to
0, the top bit is for official usage.
84 Bits
15 thru
23 are reserved.
88 Bits
24 thru
31 are for custom usage.
92 bit
6 (
\textbf{B
}) is endian-selection: LE/BE
106 0b0000 STANDARD (
2019) RVC
126 0b1000 custom
16 bit opcode meanings
1
130 0b1001 custom
16 bit opcode meanings
2
148 when bit
0 is
1,
\textbf{Foreign arch
} mode is selected.
152 Bits
1 thru
7 are a table of foreign arches.
156 when the MSB is
1, this is for custom use.
160 when the MSB is
0, bits
1 thru
6 are reserved for
64 possible official foreign archs.
166 Foreign archs could be (examples):
194 0b0010000 Java Bytecode
198 0b0010001 N.E.Other Bytecode
206 0b1000000 custom foreign arch
1
210 0b1000001 custom foreign arch
2
220 Note that
\textbf{official
} foreign archs have a binary value where the MSB is zero,
221 and custom foreign archs have a binary value where the MSB is
1.
223 \section{Namespaces are permitted to swap to new state
} \label{stateswap
}
227 In each privilege level, on a change of ISANS (whether through manual setting
228 of ISANS or through trap entry or exit changing the ISANS CSR), an
229 implementation is permitted to completely and arbitrarily switch not only the
230 instruction set, it is permitted to switch to a new bank of CSRs (or a subset
231 of the same), and even to switch to a new PC.
235 This to occur immediately and atomically at the point at which the change in ISANS occurs.
239 The most obvious application of this is for Foreign Archs, which may have their
240 own completely separate PC. Thus, foreign assembly code and RISCV assembly code
241 need not be mixed in the same binary.
245 Further use-cases may be envisaged however great care needs to be taken to not
246 cause massive complications for JIT emulation, as the RV ISANS is unary encoded
247 (
2\^
31 permutations).
251 In addition, the state information of
\textbf{all
} namespaces has to be saved
252 and restored on a context-switch (unless the SP is also switched as part of the
253 state!) which is quite severely burdensome and getting exceptionally complex.
257 Switching CSR, PC (and potentially SP) and other state on a NS change in the
258 RISCV unary NS therefore needs to be done wisely and responsibly, i.e.
263 To be discussed. Context
264 href=https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/x-uFZDXiOxY/
27QDW5KvBQAJ
267 \section{Privileged Modes / Traps
} \label{privtraps
}
271 An additional WLRL CSR per priv-level named
\textbf{LAST-ISANS
} is required, and
272 another called
\textbf{TRAP-ISANS
}
273 These mirrors the ISANS CSR, and, on a trap, the current ISANS in
274 that privilege level is atomically
275 transferred into LAST-ISANS by the hardware, and ISANS in that trap
276 is set to TRAP-ISANS. Hardware is
\textbf{only then
} permitted to modify the PC to
277 begin execution of the trap.
281 On exit from the trap, LAST-ISANS is copied into the ISANS CSR, and
282 LAST-ISANS is set to TRAP-ISANS.
\textbf{Only then
} is the hardware permitted
283 to modify the PC to begin execution where the trap left off.
287 This is identical to how xepc is handled.
291 Note
1: in the case of Supervisor Mode (context switches in particular),
292 saving and changing of LAST-ISANS (to and from the stack) must be done
293 atomically and under the protection of the SIE bit. Failure to do so
294 could result in corruption of LAST-ISANS when multiple traps occur in
295 the same privilege level.
299 Note
2: question - should the trap due to illegal (unsupported) values
300 written into LAST-ISANS occur when the
\textbf{software
} writes to LAST-ISANS,
301 or when the
\textbf{trap
} (on exit) writes into LAST-ISANS? this latter seems
302 fraught: a trap, on exit, causing another trap??
306 Per-privilege-level pseudocode (there exists UISANS, UTRAPISANS, ULASTISANS,
307 MISANS, MTRAPISANS, MLASTISANS and so on):
312 LAST-ISANS = ISANS // record the old NS
313 ISANS = TRAP_ISANS // traps are executed in "trap" NS
321 LAST-ISANS = TRAP_ISANS
325 \section{Alternative RVC
16 Bit Opcode meanings
} \label{alternativervc16bitopcodemeanings
}
329 Here is appropriate to raise an idea how to cover RVC and future
330 variants, including RV16.
334 Just as with foreign archs, and you quite rightly highlight above, it
335 makes absolutely no sense to try to select both RVCv1, v2, v3 and so on,
336 all simultaneously. An unary bit vector for RVC modes, changing the
16
337 BIT opcode space meaning, is wasteful and again has us believe that WARL
338 is the
\textbf{solution
}.
342 The correct thing to do is, again, just like with foreign archs, to
343 treat RVCs as a
\textbf{binary
} namespace selector. Bits
1 thru
3 would give
344 8 possible completely new alternative meanings, just like how the Z80
345 and the
286 and
386 used to do bank switching.
349 All zeros is clearly reserved for the present RVC.
0b001 for RVCv2.
0b010
350 for RV16 (look it up) and there should definitely be room reserved here
351 for custom reencodings of the
16 bit opcode space.
353 \section{FAQ
}\label{faq
}
355 \subsection{Why not have TRAP-ISANS as a vector table, matching mtvec?
} \label{trap-isans-vec
}
359 Use case to be determined. Rather than be a global per-priv-level value,
360 TRAP-ISANS is a table of length exactly equal to the mtvec/utvec/stvec table,
361 with corresponding entries that specify the assembly-code namespace in which
362 the trap handler routine is written.
366 Open question: see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IAhyOqEZoWA/BM0G3J2zBgAJ
371 LAST-ISANS = ISANS // record the old NS
372 ISANS = TRAP_ISANS_VEC
[xcause
] // traps are executed in "trap" NS
380 LAST-ISANS = TRAP_ISANS_VEC
[x_cause
]
384 \subsection{Is this like MISA?
} \label{misa
}
396 MISA's space is entirely taken up (and running out).
400 There is no allocation (provision) for custom extensions.
404 MISA switches on and off entire extensions: ISAMUX/NS may be used to switch
405 multiple opcodes (present and future), to alternate meanings.
409 MISA is WARL and is inaccessible from everything but M-Mode (not even readable).
415 MISA is therefore wholly unsuited to U-Mode usage; ISANS is specifically
416 permitted to be called by userspace to switch (with no stalling) between
417 namespaces, repeatedly and in quick succession.
419 \subsection{What happens if this scheme is not adopted? Why is it better than leaving things well alone?
} \label{laissezfaire
}
423 At the first sign of an emergency non-backwards compatible and unavoidable
424 change to the
\textbf{frozen
} RISCV
\textbf{official
} Standards, the entire RISCV
425 community is fragmented and divided into two:
433 Those vendors that are hardware compatible with the legacy standard.
437 Those that are compatible with the new standard.
443 \textbf{These two communities would be mutually exclusively incompatible
}. If
444 a second emergency occurs, RISCV becomes even less tenable.
448 Hardware that wished to be
\textbf{compatible
} with either flavour would require
449 JIT or offline static binary recompilation. No vendor would willingly
450 accept this as a condition of the standards divergence in the first place,
451 locking up decision making to the detriment of RISCV as a whole.
455 By providing a
\textbf{safety valve
} in the form of a hidden namespace, at least
456 newer hardware has the option to implement both (or more) variations,
457 \textbf{and still apply for Certification
}.
461 However to also allow
\textbf{legacy
} hardware to at least be JIT soft
462 compatible, some very strict rules
\textbf{must
} be adhered to, that appear at
463 first sight not to make any sense.
467 It's complicated in other words!
469 \subsection{Surely it's okay to just tell people to use
48-bit encodings?
} \label{use48bit
}
473 Short answer: it doesn't help resolve conflicts, and costs hardware and
474 redesigns to do so. Softcores in cost-sensitive embedded applications may
475 even not actually be able to fit the required
48 bit instruction decode engine
476 into a (small, ICE40) FPGA.
48-bit instruction decoding is much more complex
477 than straight
32-bit decoding, requiring a queue.
481 Second answer: conflicts can still occur in the (unregulated, custom)
48-bit
482 space, which
\textbf{could
} be resolved by ISAMUX/ISANS as applied to the
\textbf{48} bit
483 space in exactly the same way. And the
64-bit space.
485 \subsection{Why not leave this to individual custom vendors to solve on a case by case basis?
} \label{case-by-case
}
489 The suggestion was raised that a custom extension vendor could create
490 their own CSR that selects between conflicting namespaces that resolve
491 the meaning of the exact same opcode. This to be done by all and any
492 vendors, as they see fit, with little to no collaboration or coordination
493 towards standardisation in any form.
497 The problems with this approach are numerous, when presented to a
498 worldwide context that the UNIX Platform, in particular, has to face
499 (where the embedded platform does not)
503 First: lack of coordination, in the proliferation of arbitrary solutions,
504 has to primarily be borne by gcc, binutils, LLVM and other compilers.
508 Secondly: CSR space is precious. With each vendor likely needing only one
509 or two bits to express the namespace collision avoidance, if they make
510 even a token effort to use worldwide unique CSRs (an effort that would
511 benefit compiler writers), the CSR register space is quickly exhausted.
515 Thirdly: JIT Emulation of such an unregulated space becomes just as
516 much hell as it is for compiler writers. In addition, if two vendors
517 use conflicting CSR addresses, the only sane way to tell the emulator
518 what to do is to give the emulator a runtime commandline argument.
522 Fourthly: with each vendor coming up with their own way of handling
523 conflicts, not only are the chances of mistakes higher, it is against the
524 very principles of collaboration and cooperation that save vendors money
525 on development and ongoing maintenance. Each custom vendor will have
526 to maintain their own separate hard fork of the toolchain and software,
527 which is well known to result in security vulnerabilities.
531 By coordinating and managing the allocation of namespace bits (unary
532 or binary) the above issues are solved. CSR space is no longer wasted,
533 compiler and JIT software writers have an easier time, clashes are
534 avoided, and RISCV is stabilised and has a trustable long term future.
536 \subsection{ Why ISAMUX / ISANS has to be WLRL and mandatory trap on illegal writes
} \label{wlrlmandatorytrap
}
540 The namespaces, set by bits in the CSR, are functionally directly
541 equivalent to c++ namespaces, even down to the use of braces.
545 WARL, by allowing implementors to choose the value, prevents and prohibits
546 the critical and necessary raising of an exception that would begin the
547 JIT process in the case of ongoing standards evolution.
551 Without this opportunity, an implementation has no reliable guaranteed way of knowing
552 when to drop into full JIT mode,
553 which is the only guaranteed way to distinguish
554 any given conflicting opcode. It is as if the c++
555 standard was given a similar optional
556 opportunity to completely ignore the
557 \textbf{using namespace
} prefix!
565 Ok so I trust it's now clear why WLRL (thanks Allen) is needed.
569 When Dan raised the WARL concern initially a situation was masked by
570 the conflict, that if gone unnoticed would jeapordise ISAMUX/ISANS
571 entirely. Actually, two separate errors. So thank you for raising the
576 The situation arises when foreign archs are to be given their own NS
577 bit. MIPS is allocated bit
8, x86 bit
9, whilst LE/BE is given bit
0,
578 RVCv2 bit
1 andso on. All of this potential rather than actual, clearly.
582 Imagine then that software tries to write and set not just bit
8 and
583 bit
9, it also tries to set bit
0 and
1 as well.
587 This
\textbf{IS
} on the face of it a legitimate reason to make ISAMUX/ISANS WARL.
591 However it masks a fundamental flaw that has to be addressed, which
592 brings us back much closer to the original design of
18 months ago,
593 and it's highlighted thus:
597 x86 and simultaneous RVCv2 modes are total nonsense in the first place!
601 The solution instead is to have a NS bit (bit0) that SPECIFICALLY
602 determines if the arch is RV or not. If
0, the rest of the ISAMUX/ISANS
603 is very specifically RV
\textbf{only
}, and if
1, the ISAMUX/ISANS is a
\textbf{binary
}
604 table of foreign architectures and foreign architectures only.
608 Exactly how many bits are used for the foreign arch table, is to
609 be determined.
7 bits, one of which is reserved for custom usage,
610 leaving a whopping
64 possible
\textbf{official
} foreign instruction sets to
611 be hardware-supported/JIT-emulated seems to be sufficiently gratuitous,
616 One of those could even be Java Bytecode!
620 Now, it could
\textbf{hypothetically
} be argued that the permutation of setting
621 LE/BE and MIPS for example is desirable. A simple analysis shows this
622 not to be the case: once in the MIPS foreign NS, it is the MIPS hardware
623 implementation that should have its own way of setting and managing its
624 LE/BE mode, because to do otherwise drastically interferes with MIPS
625 binary compatibility.
629 Thus, it is officially Not Our Problem: only flipping into one foreign
630 arch at a time makes sense, thus this has to be reflected in the
631 ISAMUX/ISANS CSR itself, completely side-stepping the (apparent) need
632 to make the NS CSR WARL (which would not work anyway, as previously
637 So, thank you, again, Dan, for raising this. It would have completely
638 jeapordised ISAMUX/NS if not spotted.
642 The second issue is: how does any hardware system, whether it support
643 ISANS or not, and whether any future hardware supports some Namespaces
644 and, in a transitive fashion, has to support
\textbf{more
} future namespaces,
645 through JIT emulation, if this is not planned properly in advance?
649 Let us take the simple case first: a current
2019 RISCV fully compliant
650 RV64GC UNIX capable system (with mandatory traps on all unsupported CSRs).
654 Fast forward
20 years, there are now
5 ISAMUX/NS unary bits, and
3
655 foreign arch binary table entries.
659 Such a system is perfectly possible of software JIT emulating ALL of these
660 options because the write to the (illegal, for that system) ISAMUX/NS
661 CSR generates the trap that is needed for that system ti begin JIT mode.
665 (This again emphasises exactly why the trap is mandatory).
669 Now let us take the case of a hypothetical system from say
2021 that
670 implements RVCv2 at the hardware level.
674 Fast forward
20 years: if the CSR were made WARL, that system would be
675 absolutely screwed. The implementor would be under the false impression
676 that ignoring setting of
\textbf{illegal
} bits was acceptable, making the
677 transition to JIT mode flat-out impossible to detect.
681 When this is considered transitively, considering all future additions to
682 the NS, and all permutations, it can be logically deduced that there is
683 a need to reserve a
\textbf{full
} set of bits in the ISAMUX/NS CSR
\textbf{in advance
}.
687 i.e. that
\textbf{right now
}, in the year
2019, the entire ISAMUX/NS CSR cannot
688 be added to piecemeal, the full
32 (or
64) bits
\textbf{has
} to be reserved,
689 and reserved bits set at zero.
693 Furthermore, if any software attempts to write to those reserved bits,
694 it
\textbf{must
} be treated just as if those bits were distinct and nonexistent
695 CSRs, and a trap raised.
699 It makes more sense to consider each NS as having its own completely
700 separate CSR, which, if it does not exist, clearly it should be obvious
701 that, as an unsupported CSR, a trap should be raised (and JIT emulation
706 However given that only the one bit is needed (in RV NS Mode, not
707 Foreign NS Mode), it would be terribly wasteful of the CSRs to do this,
708 despite it being technically correct and much easier to understand why
709 trap raising is so essential (mandatory).
713 This again should emphasise how to mentally get one's head round this
714 mind-bendingly complex problem space: think of each NS bit as its own
715 totally separate CSR that every implementor is free and clear to implement
716 (or leave to JIT Emulation) as they see fit.
720 Only then does the mandatory need to trap on write really start to hit
721 home, as does the need to preallocate a full set of reserved zero values
726 Lastly, I
\textbf{think
} it's ok to only reserve say
32 bits, and, in
50 years
727 time if that genuinely is not enough, start the process all over again
728 with a new CSR. ISAMUX2/NS2.
732 Subdivision of the RV NS (support for RVCv3/
4/
5/RV16 without wasting
733 precious CSR bits) best left for discussion another time, the above is
734 a heck of a lot to absorb, already.
736 \subsection{Why WARL will not work and why WLRL is required
}
740 WARL requires a follow-up read of the CSR to ascertain what heuristic
741 the hardware
\textbf{might
} have applied, and if that procedure is followed in
742 this proposal, performance even on hardware would be severely compromised.
746 In addition when switching to foreign architectures, the switch has to
747 be done atomically and guaranteed to occur.
751 In the case of JIT emulation, the WARL
\textbf{detection
} code will be in an
752 assembly language that is alien to hardware.
756 Support for both assembly languages immediately after the CSR write
757 is clearly impossible, this leaves no other option but to have the CSR
758 be WLRL (on all platforms) and for traps to be mandatory (on the UNIX
761 \subsection{Is it strictly necessary for foreign archs to switch back?
} \label{foreignswitch
}
765 No, because LAST-ISANS handles the setting and unsetting of the ISANS CSR
766 in a completely transparent fashion as far as the foreign arch is concerned.
767 Supervisor or Hypervisor traps take care of the context switch in a way
768 that the user mode (or guest) need not be aware of, in any way.
772 Thus, in e.g. Hypervisor Mode, the foreign guest arch has no knowledge
773 or need to know that the hypervisor is flipping back to RV at the time of
778 Note however that this is
\textbf{not
} the same as the foreign arch executing
779 \textbf{foreign
} traps! Foreign architecture trap and interrupt handling mechanisms
780 are
\textbf{out of scope
} of this
document and MUST be handled by the foreign
781 architecture implementation in a completely transparent fashion that in
782 no way interacts or interferes with this proposal.
784 \subsection{Can we have dynamic declaration and runtime declaration of capabilities?
} \label{dynamic
}
788 Answer: don't know (yet). Quoted from Rogier:
791 "A SOC may have several devices that one may want to directly control
792 with custom instructions. If independent vendors use the same opcodes you
793 either have to change the encodings for every different chip (not very
794 nice for software) or you can give the device an ID which is defined in
795 some device tree or something like that and use that."
800 dynamic detection wasn't originally planned: static
801 compilation was envisaged to solve the need, with a table of
802 mvendorid-marchid-isamux/isans being maintained inside gcc / binutils /
803 llvm (or separate library?) that, like the linux kernel ARCH table,
804 requires a world-wide atomic
\textbf{git commit
} to add globally-unique
805 registered entries that map functionality to actual namespaces.
809 where that goes wrong is if there is ever a pair (or more) of vendors
810 that use the exact same custom feature that maps to different opcodes,
811 a statically-compiled binary has no hope of executing natively on both
816 at that point: yes, something akin to device-tree would be needed.
818 \section{Open Questions
}\label{open-questions
}
822 This section from a post by Rogier Bruisse
823 \href{http://hands.com/~lkcl/gmail_re_isadev_isamux.html
}{http://hands.com/~lkcl/gmail
\_re\_isadev\_isamux.html
}
825 \subsection{is the ISANS CSR a
32 or XLEN bit value?
} \label{isans-
32-or-xlen
}
829 This is partly answered in another FAQ above: if
32 bits is not enough
830 for a full suite of official, custom-with-atomic-registration and custom-without
831 then a second CSR group (ISANS2) may be added at a future date (
10-
20 years
836 32 bits would not inconvenience RV32, and implementors wishing to
837 make significant altnernative modifications to opcodes in the RV32 ISA space
838 could do so without the burden of having to support a split
32/LO
32/HI
839 CSR across two locations.
841 \subsection{Is the ISANS a flat number space or should some bits be reserved for use as flags?
}
845 See
16-bit RV namespace "page" concept, above. Some bits have to be unary
846 (multiple simultaneous features such as LE/BE in one bit, and augmented
847 Floating-point rounding / clipping in another), whilst others definitely
848 need to be binary (the most obvious one being
\textbf{paging
} in the space currently
851 \subsection{Should the ISANS space be partitioned between reserved, custom with registration guaranteed non clashing, custom, very likely non clashing?
}
857 \subsection{Should only compiler visible/generated constant setting with CSRRWI and/or using a clearly recognisable LI/LUI be accommodated or should dynamic setting be accommodated as well?
}
861 This is almost certainly a software design issue, not so much a hardware
864 \subsection{How should the ISANS be (re)stored in a trap and in context switch?
}
868 See section above on privilege mode: LAST-ISANS has been introduced that
869 mirrors (x)CAUSE and (x)EPC pretty much exactly. Context switches change
870 uepc just before exit from the trap, in order to change the user-mode PC
871 to switch to a new process, and ulast-isans can - must - be treated in
872 exactly the same way. When the context switch sets ulast-isans (and uepc),
873 the hardware flips both ulast-isans into uisans and uepc into pc (atomically):
874 both the new NS and the new PC activate immediately, on return to usermode.
880 \subsection{Should the mechanism accommodate "foreign ISA's" and if so how does one restore the ISA.
}
884 See section above on LAST-ISANS. With the introduction of LAST-ISANS, the
885 change is entirely transparent, and handled by the Supervisor (or Hypervisor)
886 trap, in a fashion that the foreign ISA need not even know of the existence
889 \subsection{Where is the default ISA stored and what is responsible for what it is after
}
908 calling into a dynamically linked library
916 changing privilege levels
922 These first four are entirely at the discretion of (and the
923 responsibility of) the software. There is precedent for most of these
924 having been implemented, historically, at some point, in relation to
925 LE/BE mode CSRs in other hardware (MIPSEL vs MIPS distros for example).
929 Traps are responsible for saving LAST-ISANS on the stack, exactly as they
930 are also responsible for saving other context-sensitive information such
931 as the registers and xEPC.
935 The hardware is responsible for atomically switching out ISANS into the
936 relevant xLAST-ISANS (and back again on exit). See Privileged Traps,
939 \subsection{If the ISANS is just bits of an instruction that are to be prefixed by the cpu, can those bits contain immediates? Register numbers?
}
943 The concept of a CSR containing an immediate makes no sense. The concept
944 of a CSR containing a register number, the contents of which would, presumably,
945 be inserted into the NS, would immediately make that register a permanent
946 and irrevocably reserved register that could not be utilised for any other
951 This is what the CSRs are supposed to be for!
955 It would be better just to have a second CSR - ISANS2 - potentially even ISANS3
956 in
60+ years time, rather than try to use a GPR for the purposes for which CSRs
959 \subsection{How does the system indicate a namespace is not recognised? Does it trap or can/must a recoverable mechanism be provided?
}
963 It doesn't "indicate" that a namespace is not recognised. WLRL fields only
964 hold supported values. If the hardware cannot hold the value, a trap
965 \textbf{MUST
} be thrown (in the UNIX platform), and at that point it becomes the
966 responsibility of software to deal with it.
968 \subsection{What are the security implications? Can some ISA namespaces be set by user space?
}
972 Of course they can. It becomes the responsibility of the Supervisor Mode
973 (the kernel) to treat ISANS in a fashion orthogonal to the PC. If the OS
974 is not capable of properly context-switching securely by setting the right
975 PC, it's not going to be capable of properly looking after changes to ISANS.
977 \subsection{Does the validity of an ISA namespace depend on privilege level? If so how?
}
981 The question does not exactly make sense, and may need a re-reading of the
982 section on how Privilege Modes, above. In RISC-V, privilege modes do not
983 actually change very much state of the system: the absolute minimum changes
984 are made (swapped out) - xEPC, xSTATUS and so on - and the privilege mode
985 is expected to handle the context switching (or other actions) itself.
989 ISANS - through LAST-ISANS - is absolutely no different. The trap and the
990 kernel (Supervisor or Hypervisor) are provided the
\textbf{mechanism
} by which
991 ISA Namespace
\textbf{may
} be set: it is up to the software to use that mechanism
992 correctly, just as the software is expected to use the mechanisms provided
993 to correctly implement context-switching by saving and restoring register
994 files, the PC, and other state. The NS effectively becomes just another