% ISAMUX
% https://bugs.libre-soc.org/show_bug.cgi?id=214
-\chapter{Introduction}
+\chapter{ISAMUX}
\paragraph{}
\item
-bit 6 (\textbf{B}) is endian-selection: LE/BE
+bit 6 (\textbf{B}) is \gls{endian}-selection: \gls{LE}/\gls{BE}
\end{itemize}
\item
-when bit 0 is 1, \textbf{Foreign arch} mode is selected.
+when bit 0 (the \gls{LSB}) is 1, \textbf{Foreign arch} mode is selected.
+% part of the reason for having LSB here is to avoid glossary ordering problems
\item
\item
-when the MSB is 1, this is for custom use.
+when the \gls{MSB} is 1, this is for custom use.
\item
\paragraph{}
-Switching \gls{CSR}, PC (and potentially SP) and other state on a NS change in the
+Switching \gls{CSR}, \gls{PC} (and potentially \gls{SP}) and other state on a NS change in the
RISCV unary NS therefore needs to be done wisely and responsibly, i.e.
minimised!
\paragraph{}
To be discussed. Context
-href=https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/x-uFZDXiOxY/27QDW5KvBQAJ
+href=https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/\\
+x-uFZDXiOxY/27QDW5KvBQAJ
\section{Privileged Modes / Traps} \label{privtraps}
These mirrors the ISANS CSR, and, on a trap, the current ISANS in
that privilege level is atomically
transferred into LAST-ISANS by the hardware, and ISANS in that trap
-is set to TRAP-ISANS. Hardware is \textbf{only then} permitted to modify the PC to
+is set to TRAP-ISANS. Hardware is \textbf{only then} permitted to modify the \gls{PC} to
begin execution of the trap.
\paragraph{}
\paragraph{}
-Open question: see https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IAhyOqEZoWA/BM0G3J2zBgAJ
+Open question: see https://groups.google.com/a/groups.riscv.org/d/msg/isa\-dev/IAhyOqEZoWA/BM0G3J2zBgAJ
\begin{verbatim}
trap_entry(x_cause)
}
\end{verbatim}
-\subsection{Is this like \gls{MISA} ?} \label{misa}
+\subsection{Is this like MISA ?} \label{misa}
\paragraph{}
\item
-MISA's space is entirely taken up (and running out).
+\gls{MISA}'s space is entirely taken up (and running out).
\item