soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
authorJędrzej Boczar <jboczar@antmicro.com>
Wed, 22 Jul 2020 14:57:51 +0000 (16:57 +0200)
committerJędrzej Boczar <jboczar@antmicro.com>
Wed, 22 Jul 2020 15:16:33 +0000 (17:16 +0200)
commit367eb1224094fea995ba19181b9e9fa3a1c56f75
tree758e96e72927d7502b14c6dc2614edfbf7c1c38e
parent8ae501c391174b6ae59b96dd01c2bde262030b0f
soc/integration: use AXILiteSRAM when using bus_standard="axi-lite"
litex/soc/integration/soc.py