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(parent: a164451) | patch
integration/soc/add_sdram: update rules to connect main bus to dram.
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 5 Aug 2020 16:01:12 +0000 (18:01 +0200)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Wed, 5 Aug 2020 16:01:12 +0000 (18:01 +0200)
commit9a4c5aa1ef6f0df74310f92b2f9112692ec5ebc7
tree2e2036aa55146b3f4fe234c4a41c71f42c85300ctree
parenta1644510bfdd86fe050c30e9204d1f768b28bf4ccommit | diff
integration/soc/add_sdram: update rules to connect main bus to dram.

Requires connection when CPU does not have memory buses of when CPU has memory buses
but no DMA bus.
litex/soc/integration/soc.py diff | blob | history